dri-devel September 2020

dri-devel@lists.freedesktop.org

359 participants
868 discussions

[PATCH v2 00/11] amd/display: Add GFX9+ modifier support.
by Bas Nieuwenhuizen 07 Sep '20

07 Sep '20

This adds modifier support to radeonsi. It has been tested on - VEGA10, RAVEN, NAVI14 - weston, sway, X with xf86-video-amdgpu (i.e. legacy path still works) and includes some basic testing of the layout code. The main goal is to keep it somewhat simple and regression free, so on the display side this series only exposes what the current GPU can render to. While we could expose more I think that is more suitable for follow-up work as the benefit would be minimal and there are some more … [View More]design discussion there to discuss that are orthogonal from the initial implementation. Similarly this series only exposes 32-bpp displayable DCC in the cases that radeonsi would use it and any extra capabilities here should be future work. I believe these are by far the most complicated modifiers we've seen up till now, mostly related to - GPU identification for cases where it matters wrt tiling. - Every generation having tiling layout changes - Compression settings. I believe the complexity is necessary as every layout should be different and all layouts should be the best in some situation (though not all combinations of GPU parameters will actually have an existing GPU). That said, on the render side the number of modifiers actually listed for a given GPU is ~10, and in the current implementation that is the same for the display side. (we could expose more actually differing layouts on the display side for cross-GPU compatibility, but I consider that out of scope for this initial work). This series can be found on https://github.com/BNieuwenhuizen/linux/tree/modifiers An userspace implementation in radeonsi can be found on https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176 v2: Per suggestion from Daniel Vetter I added logic to get the tiling_flags at addfb2 time and convert them into modifiers for GFX9+. Furthermore, the DCC constant econding modifers only get exposed on RAVEN2 and newer. Bas Nieuwenhuizen (11): drm/amd/display: Do not silently accept DCC for multiplane formats. drm/amd: Init modifier field of helper fb. drm/amd/display: Honor the offset for plane 0. drm/fourcc: Add AMD DRM modifiers. drm/amd/display: Store tiling_flags in the framebuffer. drm/amd/display: Convert tiling_flags to modifiers. drm/amd/display: Refactor surface tiling setup. drm/amd/display: Set DC options from modifiers. drm/amd/display: Add formats for DCC with 2/3 planes. drm/amd/display: Expose modifiers. drm/amd/display: Clean up GFX9 tiling_flags path. drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 169 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 754 ++++++++++++++---- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 - include/uapi/drm/drm_fourcc.h | 115 +++ 6 files changed, 880 insertions(+), 165 deletions(-) -- 2.28.0 [View Less]

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[PATCH 0/3] drm/msm/dsi: support SM8150 and SM8250
by Jonathan Marek 07 Sep '20

07 Sep '20

Add support for SM8150 and SM8250 DSI. Note I haven't tested SM8150 recently, but DSI is almost identical to SM8250. Jonathan Marek (3): drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_timing drm/msm/dsi: add DSI config for sm8150 and sm8250 drm/msm/dsi: add support for 7nm DSI PHY/PLL .../devicetree/bindings/display/msm/dsi.txt | 6 +- drivers/gpu/drm/msm/Kconfig | 7 + drivers/gpu/drm/msm/Makefile | 2 + drivers/gpu/drm/msm/dsi/… [View More]

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[PATCH] drm/doc: Document that modifiers are always required for fb
by Daniel Vetter 07 Sep '20

07 Sep '20

Even for legacy userspace, since otherwise GETFB2 is broken and if you switch between modifier-less and modifier-aware compositors, smooth transitions break. Also it's just best practice to make sure modifiers are invariant for a given drm_fb, and that a modifier-aware kms drivers only has one place to store them, ignoring any old implicit bo flags or whatever else might float around. Motivated by some irc discussion with Bas about amdgpu modifier support. Fixes: 455e00f1412f ("drm: Add … [View More]

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[PULL] drm-intel-gt-next
by Joonas Lahtinen 07 Sep '20

07 Sep '20

Hi Dave & Daniel, Exactly same content as previous PR: https://lists.freedesktop.org/archives/intel-gfx/2020-September/247626.html Just rebased adding the missing S-o-b:s and updated "Fixes:" tags accordingly as requested. Regards, Joonas *** drm-intel-gt-next-2020-09-07: (Same content as drm-intel-gt-next-2020-09-04-3, S-o-b's added) UAPI Changes: (- Potential implicit changes from WW locking refactoring) Cross-subsystem Changes: (- WW locking changes should align the i915 locking … [View More]more with others) Driver Changes: - MAJOR: Apply WW locking across the driver (Maarten) - Reverts for 5 commits to make applying WW locking faster (Maarten) - Disable preparser around invalidations on Tigerlake for non-RCS engines (Chris) - Add missing dma_fence_put() for error case of syncobj timeline (Chris) - Parse command buffer earlier in eb_relocate(slow) to facilitate backoff (Maarten) - Pin engine before pinning all objects (Maarten) - Rework intel_context pinning to do everything outside of pin_mutex (Maarten) - Avoid tracking GEM context until registered (Cc: stable, Chris) - Provide a fastpath for waiting on vma bindings (Chris) - Fixes to preempt-to-busy mechanism (Chris) - Distinguish the virtual breadcrumbs from the irq breadcrumbs (Chris) - Switch to object allocations for page directories (Chris) - Hold context/request reference while breadcrumbs are active (Chris) - Make sure execbuffer always passes ww state to i915_vma_pin (Maarten) - Code refactoring to facilitate use of WW locking (Maarten) - Locking refactoring to use more granular locking (Maarten, Chris) - Support for multiple pinned timelines per engine (Chris) - Move complication of I915_GEM_THROTTLE to the ioctl from general code (Chris) - Make active tracking/vma page-directory stash work preallocated (Chris) - Avoid flushing submission tasklet too often (Chris) - Reduce context termination list iteration guard to RCU (Chris) - Reductions to locking contention (Chris) - Fixes for issues found by CI (Chris) The following changes since commit 3393649977f9a8847c659e282ea290d4b703295c: Merge tag 'drm-intel-next-2020-08-24-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2020-08-28 14:09:31 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-gt-next-2020-09-07 for you to fetch changes up to e0ee152fce25dc9269c7ea5280c98aa4b3682759: drm/i915: Unlock the shared hwsp_gtt object after pinning (2020-09-07 15:08:11 +0300) ---------------------------------------------------------------- (Same content as drm-intel-gt-next-2020-09-04-3, S-o-b's added) UAPI Changes: (- Potential implicit changes from WW locking refactoring) Cross-subsystem Changes: (- WW locking changes should align the i915 locking more with others) Driver Changes: - MAJOR: Apply WW locking across the driver (Maarten) - Reverts for 5 commits to make applying WW locking faster (Maarten) - Disable preparser around invalidations on Tigerlake for non-RCS engines (Chris) - Add missing dma_fence_put() for error case of syncobj timeline (Chris) - Parse command buffer earlier in eb_relocate(slow) to facilitate backoff (Maarten) - Pin engine before pinning all objects (Maarten) - Rework intel_context pinning to do everything outside of pin_mutex (Maarten) - Avoid tracking GEM context until registered (Cc: stable, Chris) - Provide a fastpath for waiting on vma bindings (Chris) - Fixes to preempt-to-busy mechanism (Chris) - Distinguish the virtual breadcrumbs from the irq breadcrumbs (Chris) - Switch to object allocations for page directories (Chris) - Hold context/request reference while breadcrumbs are active (Chris) - Make sure execbuffer always passes ww state to i915_vma_pin (Maarten) - Code refactoring to facilitate use of WW locking (Maarten) - Locking refactoring to use more granular locking (Maarten, Chris) - Support for multiple pinned timelines per engine (Chris) - Move complication of I915_GEM_THROTTLE to the ioctl from general code (Chris) - Make active tracking/vma page-directory stash work preallocated (Chris) - Avoid flushing submission tasklet too often (Chris) - Reduce context termination list iteration guard to RCU (Chris) - Reductions to locking contention (Chris) - Fixes for issues found by CI (Chris) ---------------------------------------------------------------- Chris Wilson (33): drm/i915: Reduce i915_request.lock contention for i915_request_wait drm/i915/selftests: Mock the status_page.vma for the kernel_context drm/i915: Soften the tasklet flush frequency before waits drm/i915/gem: Remove disordered per-file request list for throttling drm/i915/gt: Disable preparser around xcs invalidations on tgl drm/i915/gt: Delay taking the spinlock for grabbing from the buffer pool drm/i915/selftests: Flush the active barriers before asserting drm/i915/gt: Fix termination condition for freeing all buffer objects drm/i915/gem: Delay tracking the GEM context until it is registered drm/i915/gt: Support multiple pinned timelines drm/i915/gt: Pull release of node->age under the spinlock drm/i915/selftests: Drop stale timeline constructor assert drm/i915: Skip taking acquire mutex for no ref->active callback drm/i915: Export a preallocate variant of i915_active_acquire() drm/i915: Keep the most recently used active-fence upon discard drm/i915: Make the stale cached active node available for any timeline drm/i915: Reduce locking around i915_active_acquire_preallocate_barrier() drm/i915: Provide a fastpath for waiting on vma bindings drm/i915: Remove requirement for holding i915_request.lock for breadcrumbs drm/i915/gt: Replace intel_engine_transfer_stale_breadcrumbs drm/i915/gt: Only transfer the virtual context to the new engine if active drm/i915/gt: Distinguish the virtual breadcrumbs from the irq breadcrumbs drm/i915: Preallocate stashes for vma page-directories drm/i915/gt: Switch to object allocations for page directories drm/i915/gt: Shrink i915_page_directory's slab bucket drm/i915/gt: Move intel_breadcrumbs_arm_irq earlier drm/i915/gt: Hold context/request reference while breadcrumbs are active drm/i915/selftests: Prevent selecting 0 for our random width/align drm/i915/gem: Reduce context termination list iteration guard to RCU drm/i915/gem: Free the fence after a fence-chain lookup failure drm/i915: Be wary of data races when reading the active execlists drm/i915: Remove i915_request.lock requirement for execution callbacks drm/i915: Filter wake_flags passed to default_wake_function Maarten Lankhorst (23): Revert "drm/i915/gem: Async GPU relocations only" drm/i915: Revert relocation chaining commits. Revert "drm/i915/gem: Drop relocation slowpath". Revert "drm/i915/gem: Split eb_vma into its own allocation" drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. drm/i915: Remove locking from i915_gem_object_prepare_read/write drm/i915: Parse command buffer earlier in eb_relocate(slow) drm/i915: Use per object locking in execbuf, v12. drm/i915: Use ww locking in intel_renderstate. drm/i915: Add ww context handling to context_barrier_task drm/i915: Nuke arguments to eb_pin_engine drm/i915: Pin engine before pinning all objects, v5. drm/i915: Rework intel_context pinning to do everything outside of pin_mutex drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2. drm/i915: Kill last user of intel_context_create_request outside of selftests drm/i915: Convert i915_perf to ww locking as well drm/i915: Dirty hack to fix selftests locking inversion drm/i915/selftests: Fix locking inversion in lrc selftest. drm/i915: Use ww pinning for intel_context_create_request() drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v3. drm/i915: Add ww locking to vm_fault_gtt drm/i915: Add ww locking to pin_to_display_plane, v2. Thomas Hellström (1): drm/i915: Unlock the shared hwsp_gtt object after pinning drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_client_blt.c | 89 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 105 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 80 +- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 1601 +++++++++++++------- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 51 +- drivers/gpu/drm/i915/gem/i915_gem_object.h | 40 +- drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 152 +- drivers/gpu/drm/i915/gem/i915_gem_object_blt.h | 3 + drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 10 + drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 67 +- drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 9 +- .../drm/i915/gem/selftests/i915_gem_client_blt.c | 2 +- .../drm/i915/gem/selftests/i915_gem_coherency.c | 50 +- .../gpu/drm/i915/gem/selftests/i915_gem_context.c | 144 +- .../drm/i915/gem/selftests/i915_gem_execbuffer.c | 60 +- drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 45 +- drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c | 2 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 106 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 5 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 181 +-- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 305 ++-- drivers/gpu/drm/i915/gt/intel_breadcrumbs.h | 36 + drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h | 47 + drivers/gpu/drm/i915/gt/intel_context.c | 318 ++-- drivers/gpu/drm/i915/gt/intel_context.h | 13 + drivers/gpu/drm/i915/gt/intel_context_types.h | 5 +- drivers/gpu/drm/i915/gt/intel_engine.h | 20 - drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34 +- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 97 +- drivers/gpu/drm/i915/gt/intel_gt.c | 23 +- drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 103 +- .../gpu/drm/i915/gt/intel_gt_buffer_pool_types.h | 6 +- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 300 +--- drivers/gpu/drm/i915/gt/intel_gtt.h | 142 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 182 ++- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 150 +- drivers/gpu/drm/i915/gt/intel_renderstate.c | 73 +- drivers/gpu/drm/i915/gt/intel_renderstate.h | 9 +- drivers/gpu/drm/i915/gt/intel_reset.c | 1 + drivers/gpu/drm/i915/gt/intel_ring.c | 10 +- drivers/gpu/drm/i915/gt/intel_ring.h | 3 +- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 42 +- drivers/gpu/drm/i915/gt/intel_rps.c | 1 + drivers/gpu/drm/i915/gt/intel_timeline.c | 28 +- drivers/gpu/drm/i915/gt/intel_timeline.h | 24 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 +- drivers/gpu/drm/i915/gt/mock_engine.c | 30 +- drivers/gpu/drm/i915/gt/selftest_context.c | 2 + drivers/gpu/drm/i915/gt/selftest_lrc.c | 22 +- drivers/gpu/drm/i915/gt/selftest_rps.c | 30 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 10 +- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- drivers/gpu/drm/i915/gvt/cmd_parser.c | 3 +- drivers/gpu/drm/i915/gvt/scheduler.c | 17 +- drivers/gpu/drm/i915/i915_active.c | 237 ++- drivers/gpu/drm/i915/i915_active.h | 31 +- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 24 +- drivers/gpu/drm/i915/i915_gem.c | 107 +- drivers/gpu/drm/i915/i915_gem.h | 12 + drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 57 +- drivers/gpu/drm/i915/i915_request.c | 224 +-- drivers/gpu/drm/i915/i915_request.h | 8 - drivers/gpu/drm/i915/i915_sw_fence.c | 10 +- drivers/gpu/drm/i915/i915_vma.c | 65 +- drivers/gpu/drm/i915/i915_vma.h | 13 +- drivers/gpu/drm/i915/selftests/i915_gem.c | 41 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 75 +- drivers/gpu/drm/i915/selftests/i915_perf.c | 4 +- drivers/gpu/drm/i915/selftests/i915_request.c | 18 +- drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- .../gpu/drm/i915/selftests/intel_memory_region.c | 8 +- drivers/gpu/drm/i915/selftests/mock_gtt.c | 26 +- 82 files changed, 3743 insertions(+), 2206 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_breadcrumbs.h create mode 100644 drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h [View Less]

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[PATCH V2 0/2] Implement Shutdown callback for i2c
by Roja Rani Yarubandi 07 Sep '20

07 Sep '20

Store DMA mapping data in geni_i2c_dev struct. Implement Shutdown callback for geni i2c driver. Changes in V2: - Changed commit text. - As per Stephen's comments added separate function for stop transfer. Roja Rani Yarubandi (2): i2c: i2c-qcom-geni: Store DMA mapping data in geni_i2c_dev struct i2c: i2c-qcom-geni: Add shutdown callback for i2c drivers/i2c/busses/i2c-qcom-geni.c | 50 ++++++++++++++++++++++++++++++ include/linux/qcom-geni-se.h | 5 +++ 2 files changed, 55 … [View More]

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[PATCH] drm/ttm: merge offset and base in ttm_bus_placement
by Christian König 07 Sep '20

07 Sep '20

This is used by TTM to communicate the physical address which should be used with ioremap(), ioremap_wc(). We don't need to separate the base and offset in any way here. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 ++++--- drivers/gpu/drm/drm_gem_ttm_helper.c | 5 +---- drivers/gpu/drm/drm_gem_vram_helper.c | 3 +-- drivers/gpu/drm/nouveau/nouveau_bo.c | 9 ++++----- drivers/gpu/drm/nouveau/… [View More]nouveau_fbcon.c | 3 +-- drivers/gpu/drm/qxl/qxl_ttm.c | 7 +++---- drivers/gpu/drm/radeon/radeon_ttm.c | 14 ++++++-------- drivers/gpu/drm/ttm/ttm_bo.c | 3 --- drivers/gpu/drm/ttm/ttm_bo_util.c | 17 ++++++----------- drivers/gpu/drm/ttm/ttm_bo_vm.c | 3 +-- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 4 ++-- include/drm/ttm/ttm_resource.h | 6 ++---- 12 files changed, 31 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 46d620817482..b39d2a834340 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -773,7 +773,7 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + mem->bus.offset; - mem->bus.base = adev->gmc.aper_base; + mem->bus.offset += adev->gmc.aper_base; mem->bus.is_iomem = true; break; default: @@ -785,12 +785,13 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, unsigned long page_offset) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); uint64_t offset = (page_offset << PAGE_SHIFT); struct drm_mm_node *mm; mm = amdgpu_find_mm_node(&bo->mem, &offset); - return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + - (offset >> PAGE_SHIFT); + offset += adev->gmc.aper_base; + return mm->start + (offset >> PAGE_SHIFT); } /** diff --git a/drivers/gpu/drm/drm_gem_ttm_helper.c b/drivers/gpu/drm/drm_gem_ttm_helper.c index 892b2288a104..0e4fb9ba43ad 100644 --- a/drivers/gpu/drm/drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/drm_gem_ttm_helper.c @@ -43,12 +43,9 @@ void drm_gem_ttm_print_info(struct drm_printer *p, unsigned int indent, drm_print_bits(p, bo->mem.placement, plname, ARRAY_SIZE(plname)); drm_printf(p, "\n"); - if (bo->mem.bus.is_iomem) { - drm_printf_indent(p, indent, "bus.base=%lx\n", - (unsigned long)bo->mem.bus.base); + if (bo->mem.bus.is_iomem) drm_printf_indent(p, indent, "bus.offset=%lx\n", (unsigned long)bo->mem.bus.offset); - } } EXPORT_SYMBOL(drm_gem_ttm_print_info); diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index 545a877406f4..255560591916 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c +++ b/drivers/gpu/drm/drm_gem_vram_helper.c @@ -1042,8 +1042,7 @@ static int bo_driver_io_mem_reserve(struct ttm_bo_device *bdev, case TTM_PL_SYSTEM: /* nothing to do */ break; case TTM_PL_VRAM: - mem->bus.offset = mem->start << PAGE_SHIFT; - mem->bus.base = vmm->vram_base; + mem->bus.offset = (mem->start << PAGE_SHIFT) + vmm->vram_base; mem->bus.is_iomem = true; break; default: diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index f74988771ed8..4c2cc862eb19 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1081,8 +1081,8 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) case TTM_PL_TT: #if IS_ENABLED(CONFIG_AGP) if (drm->agp.bridge) { - reg->bus.offset = reg->start << PAGE_SHIFT; - reg->bus.base = drm->agp.base; + reg->bus.offset = (reg->start << PAGE_SHIFT) + + drm->agp.base; reg->bus.is_iomem = !drm->agp.cma; } #endif @@ -1094,8 +1094,8 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) } fallthrough; /* tiled memory */ case TTM_PL_VRAM: - reg->bus.offset = reg->start << PAGE_SHIFT; - reg->bus.base = device->func->resource_addr(device, 1); + reg->bus.offset = (reg->start << PAGE_SHIFT) + + device->func->resource_addr(device, 1); reg->bus.is_iomem = true; if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { union { @@ -1133,7 +1133,6 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) goto out; } - reg->bus.base = 0; reg->bus.offset = handle; ret = 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index fad8030ec1f8..3159a2172db5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -378,8 +378,7 @@ nouveau_fbcon_create(struct drm_fb_helper *helper, FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT; info->fbops = &nouveau_fbcon_sw_ops; - info->fix.smem_start = nvbo->bo.mem.bus.base + - nvbo->bo.mem.bus.offset; + info->fix.smem_start = nvbo->bo.mem.bus.offset; info->fix.smem_len = nvbo->bo.mem.num_pages << PAGE_SHIFT; info->screen_base = nvbo_kmap_obj_iovirtual(nvbo); diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index 7aae0a96f043..b20c356229c3 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -81,13 +81,12 @@ int qxl_ttm_io_mem_reserve(struct ttm_bo_device *bdev, return 0; case TTM_PL_VRAM: mem->bus.is_iomem = true; - mem->bus.base = qdev->vram_base; - mem->bus.offset = mem->start << PAGE_SHIFT; + mem->bus.offset = (mem->start << PAGE_SHIFT) + qdev->vram_base; break; case TTM_PL_PRIV: mem->bus.is_iomem = true; - mem->bus.base = qdev->surfaceram_base; - mem->bus.offset = mem->start << PAGE_SHIFT; + mem->bus.offset = (mem->start << PAGE_SHIFT) + + qdev->surfaceram_base; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 74ad50c7491c..4cfadda7be2b 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -372,8 +372,8 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso #if IS_ENABLED(CONFIG_AGP) if (rdev->flags & RADEON_IS_AGP) { /* RADEON_IS_AGP is set only if AGP is active */ - mem->bus.offset = mem->start << PAGE_SHIFT; - mem->bus.base = rdev->mc.agp_base; + mem->bus.offset = (mem->start << PAGE_SHIFT) + + rdev->mc.agp_base; mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; } #endif @@ -383,7 +383,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso /* check if it's visible */ if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size) return -EINVAL; - mem->bus.base = rdev->mc.aper_base; + mem->bus.offset += rdev->mc.aper_base; mem->bus.is_iomem = true; #ifdef __alpha__ /* @@ -392,12 +392,10 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso */ if (mem->placement & TTM_PL_FLAG_WC) mem->bus.addr = - ioremap_wc(mem->bus.base + mem->bus.offset, - bus_size); + ioremap_wc(mem->bus.offset, bus_size); else mem->bus.addr = - ioremap(mem->bus.base + mem->bus.offset, - bus_size); + ioremap(mem->bus.offset, bus_size); if (!mem->bus.addr) return -ENOMEM; @@ -407,7 +405,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso * It then can be used to build PTEs for VRAM * access, as done in ttm_bo_vm_fault(). */ - mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + + mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) + rdev->ddev->hose->dense_mem_base; #endif break; diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 89d8ab6edd40..0812f4ce40db 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -641,7 +641,6 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, evict_mem = bo->mem; evict_mem.mm_node = NULL; - evict_mem.bus.base = 0; evict_mem.bus.offset = 0; evict_mem.bus.addr = NULL; @@ -1076,7 +1075,6 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object *bo, mem.num_pages = bo->num_pages; mem.size = mem.num_pages << PAGE_SHIFT; mem.page_alignment = bo->mem.page_alignment; - mem.bus.base = 0; mem.bus.offset = 0; mem.bus.addr = NULL; mem.mm_node = NULL; @@ -1235,7 +1233,6 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, bo->mem.num_pages = bo->num_pages; bo->mem.mm_node = NULL; bo->mem.page_alignment = page_alignment; - bo->mem.bus.base = 0; bo->mem.bus.offset = 0; bo->mem.bus.addr = NULL; bo->moving = NULL; diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 2c967607d485..85b670e7c20d 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -94,7 +94,7 @@ EXPORT_SYMBOL(ttm_bo_move_ttm); int ttm_mem_io_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) { - if (mem->bus.base || mem->bus.offset || mem->bus.addr) + if (mem->bus.offset || mem->bus.addr) return 0; mem->bus.is_iomem = false; @@ -107,13 +107,12 @@ int ttm_mem_io_reserve(struct ttm_bo_device *bdev, void ttm_mem_io_free(struct ttm_bo_device *bdev, struct ttm_resource *mem) { - if (!mem->bus.base && !mem->bus.offset && !mem->bus.addr) + if (!mem->bus.offset && !mem->bus.addr) return; if (bdev->driver->io_mem_free) bdev->driver->io_mem_free(bdev, mem); - mem->bus.base = 0; mem->bus.offset = 0; mem->bus.addr = NULL; } @@ -136,11 +135,9 @@ static int ttm_resource_ioremap(struct ttm_bo_device *bdev, size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; if (mem->placement & TTM_PL_FLAG_WC) - addr = ioremap_wc(mem->bus.base + mem->bus.offset, - bus_size); + addr = ioremap_wc(mem->bus.offset, bus_size); else - addr = ioremap(mem->bus.base + mem->bus.offset, - bus_size); + addr = ioremap(mem->bus.offset, bus_size); if (!addr) { ttm_mem_io_free(bdev, mem); return -ENOMEM; @@ -427,12 +424,10 @@ static int ttm_bo_ioremap(struct ttm_buffer_object *bo, } else { map->bo_kmap_type = ttm_bo_map_iomap; if (mem->placement & TTM_PL_FLAG_WC) - map->virtual = ioremap_wc(bo->mem.bus.base + - bo->mem.bus.offset + offset, + map->virtual = ioremap_wc(bo->mem.bus.offset + offset, size); else - map->virtual = ioremap(bo->mem.bus.base + - bo->mem.bus.offset + offset, + map->virtual = ioremap(bo->mem.bus.offset + offset, size); } return (!map->virtual) ? -ENOMEM : 0; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index d3dc0682425c..eb1017af0710 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -101,8 +101,7 @@ static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo, if (bdev->driver->io_mem_pfn) return bdev->driver->io_mem_pfn(bo, page_offset); - return ((bo->mem.bus.base + bo->mem.bus.offset) >> PAGE_SHIFT) - + page_offset; + return (bo->mem.bus.offset >> PAGE_SHIFT) + page_offset; } /** diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c index c7f10b2c93d2..0adbacd29066 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c @@ -721,8 +721,8 @@ static int vmw_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resourc case VMW_PL_MOB: return 0; case TTM_PL_VRAM: - mem->bus.offset = mem->start << PAGE_SHIFT; - mem->bus.base = dev_priv->vram_start; + mem->bus.offset = (mem->start << PAGE_SHIFT) + + dev_priv->vram_start; mem->bus.is_iomem = true; break; default: diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index 406baa8f0068..7b8a3157fbb3 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -148,16 +148,14 @@ struct ttm_resource_manager { * struct ttm_bus_placement * * @addr: mapped virtual address - * @base: bus base address + * @offset: physical addr * @is_iomem: is this io memory ? - * @offset: offset from the base address * * Structure indicating the bus placement of an object. */ struct ttm_bus_placement { void *addr; - phys_addr_t base; - unsigned long offset; + phys_addr_t offset; bool is_iomem; }; -- 2.17.1 [View Less]

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[PATCH 0/2] drm: panel: add support for TDO tl070wsh30 panel
by Neil Armstrong 07 Sep '20

07 Sep '20

This adds support bindings and support for the TDO TL070WSH30 TFT-LCD panel module shipped with the Amlogic S400 Development Kit. The panel has a 1024×600 resolution and uses 24 bit RGB per pixel. It provides a MIPI DSI interface to the host, a built-in LED backlight and touch controller. Neil Armstrong (2): dt-bindings: display: panel: add TDO tl070wsh30 DSI panel bindings drm: panel: add TDO tl070wsh30 panel driver .../display/panel/tdo,tl070wsh30.yaml | 58 ++++ drivers/gpu/… [View More]

2 5

[PATCH v3 0/2] drm: fix virtio-gpu + sev
by Gerd Hoffmann 07 Sep '20

07 Sep '20

virtio-gpu must make sure scatter list segments are not too big. Gerd Hoffmann (2): drm: allow limiting the scatter list size. drm/virtio: set max_segment include/drm/drm_device.h | 8 ++++++++ include/drm/drm_prime.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 3 ++- drivers/gpu/drm/drm_gem_shmem_helper.c | 3 ++- drivers/gpu/drm/drm_prime.c | 10 +++++++--- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 3 ++- … [View More]

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[PATCH v2] drm/bridge: dw-mipi-dsi.c: Add VPG runtime config through debugfs
by Angelo Ribeiro 07 Sep '20

07 Sep '20

Add support for the video pattern generator (VPG) BER pattern mode and configuration in runtime. This enables using the debugfs interface to manipulate the VPG after the pipeline is set. Also, enables the usage of the VPG BER pattern. Changes in v2: - Added VID_MODE_VPG_MODE - Solved incompatible return type on __get and __set Reported-by: kbuild test robot <lkp(a)intel.com> Reported-by: Adrian Pop <pop.adrian61(a)gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel(a)… [View More]synopsys.com> Cc: Joao Pinto <jpinto(a)synopsys.com> Cc: Jose Abreu <jose.abreu(a)synopsys.com> Signed-off-by: Angelo Ribeiro <angelo.ribeiro(a)synopsys.com> --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 98 ++++++++++++++++++++++++--- 1 file changed, 90 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index b18351b..9de3645 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -91,6 +91,7 @@ #define VID_MODE_TYPE_BURST 0x2 #define VID_MODE_TYPE_MASK 0x3 #define VID_MODE_VPG_ENABLE BIT(16) +#define VID_MODE_VPG_MODE BIT(20) #define VID_MODE_VPG_HORIZONTAL BIT(24) #define DSI_VID_PKT_SIZE 0x3c @@ -221,6 +222,21 @@ #define PHY_STATUS_TIMEOUT_US 10000 #define CMD_PKT_STATUS_TIMEOUT_US 20000 +#ifdef CONFIG_DEBUG_FS +#define VPG_DEFS(name, dsi) \ + ((void __force *)&((*dsi).vpg_defs.name)) + +#define REGISTER(name, mask, dsi) \ + { #name, VPG_DEFS(name, dsi), mask, dsi } + +struct debugfs_entries { + const char *name; + bool *reg; + u32 mask; + struct dw_mipi_dsi *dsi; +}; +#endif /* CONFIG_DEBUG_FS */ + struct dw_mipi_dsi { struct drm_bridge bridge; struct mipi_dsi_host dsi_host; @@ -238,9 +254,12 @@ struct dw_mipi_dsi { #ifdef CONFIG_DEBUG_FS struct dentry *debugfs; - - bool vpg; - bool vpg_horizontal; + struct debugfs_entries *debugfs_vpg; + struct { + bool vpg; + bool vpg_horizontal; + bool vpg_ber_pattern; + } vpg_defs; #endif /* CONFIG_DEBUG_FS */ struct dw_mipi_dsi *master; /* dual-dsi master ptr */ @@ -530,9 +549,11 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; #ifdef CONFIG_DEBUG_FS - if (dsi->vpg) { + if (dsi->vpg_defs.vpg) { val |= VID_MODE_VPG_ENABLE; - val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0; + val |= dsi->vpg_defs.vpg_horizontal ? + VID_MODE_VPG_HORIZONTAL : 0; + val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0; } #endif /* CONFIG_DEBUG_FS */ @@ -961,6 +982,68 @@ static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { #ifdef CONFIG_DEBUG_FS +int dw_mipi_dsi_debugfs_write(void *data, u64 val) +{ + struct debugfs_entries *vpg = data; + struct dw_mipi_dsi *dsi; + u32 mode_cfg; + + if (!vpg) + return -ENODEV; + + dsi = vpg->dsi; + + *vpg->reg = (bool)val; + + mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG); + + if (*vpg->reg) + mode_cfg |= vpg->mask; + else + mode_cfg &= ~vpg->mask; + + dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg); + + return 0; +} + +int dw_mipi_dsi_debugfs_show(void *data, u64 *val) +{ + struct debugfs_entries *vpg = data; + + if (!vpg) + return -ENODEV; + + *val = *vpg->reg; + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show, + dw_mipi_dsi_debugfs_write, "%llu\n"); + +static void debugfs_create_files(void *data) +{ + struct dw_mipi_dsi *dsi = data; + struct debugfs_entries debugfs[] = { + REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi), + REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi), + REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi), + }; + int i; + + dsi->debugfs_vpg = kmalloc(sizeof(debugfs), GFP_KERNEL); + if (!dsi->debugfs_vpg) + return; + + memcpy(dsi->debugfs_vpg, debugfs, sizeof(debugfs)); + + for (i = 0; i < ARRAY_SIZE(debugfs); i++) + debugfs_create_file(dsi->debugfs_vpg[i].name, 0644, + dsi->debugfs, &dsi->debugfs_vpg[i], + &fops_x32); +} + static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL); @@ -969,14 +1052,13 @@ static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) return; } - debugfs_create_bool("vpg", 0660, dsi->debugfs, &dsi->vpg); - debugfs_create_bool("vpg_horizontal", 0660, dsi->debugfs, - &dsi->vpg_horizontal); + debugfs_create_files(dsi); } static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { debugfs_remove_recursive(dsi->debugfs); + kfree(dsi->debugfs_vpg); } #else -- 2.7.4 [View Less]

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[PATCH] drm/bridge/synopsys: dsi: add support for non-continuous HS clock
by Yannick Fertre 07 Sep '20

07 Sep '20

From: Antonio Borneo <antonio.borneo(a)st.com> Current code enables the HS clock when video mode is started or to send out a HS command, and disables the HS clock to send out a LP command. This is not what DSI spec specify. Enable HS clock either in command and in video mode. Set automatic HS clock management for panels and devices that support non-continuous HS clock. Signed-off-by: Antonio Borneo <antonio.borneo(a)st.com> --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 9 ++… [View More]

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dri-devel September 2020