dri-devel September 2020

dri-devel@lists.freedesktop.org

359 participants
868 discussions

Re: [PATCH v11 00/11] PCI: brcmstb: enable PCIe for STB chips
by Jim Quinlan 08 Sep '20

08 Sep '20

On Thu, Aug 27, 2020 at 2:35 AM Christoph Hellwig <hch(a)lst.de> wrote: > > On Tue, Aug 25, 2020 at 10:40:27AM -0700, Florian Fainelli wrote: > > Hi, > > > > On 8/24/2020 12:30 PM, Jim Quinlan wrote: > >> > >> Patchset Summary: > >> Enhance a PCIe host controller driver. Because of its unusual design > >> we are foced to change dev->dma_pfn_offset into a more general role > >> allowing multiple offsets. See the 'v1' notes below for more info. > > > > We are version 11 and counting, and it is not clear to me whether there is > > any chance of getting these patches reviewed and hopefully merged for the > > 5.10 merge window. > > > > There are a lot of different files being touched, so what would be the > > ideal way of routing those changes towards inclusion? > > FYI, I offered to take the dma-mapping bits through the dma-mapping tree. > I have a bit of a backlog, but plan to review and if Jim is ok with that > apply the current version. Sounds good to me. Thanks, Jim

3 4

[PATCH] Fixed NULL pointer dereference in handle_edid functions for GPUs that do not support EDID
by Alejandro Sior 08 Sep '20

08 Sep '20

In the function intel_vgpu_reg_rw_edid of gvt/kvmgt.c, pos can get equal to NULL for GPUs that do not properly support EDID. In those cases, when pos gets passed to the handle_edid functions, it gets added a short offset then it's dereferenced in memcpy's, leading to a kernel oops: null pointer dereference. More concretely, that kernel oops renders Broadwell GPUs users completely unable to set up virtual machines with virtual GPU passthrough (virtual machines hang indefinitely when trying to make use of the virtual GPU), and make them have huge problems when trying to remove the virtual GPUs once the kernel oops has happened (writing 1 in the vGPU remove file just makes the operation hang undefinitely, again, and the kernel is unable to shutdown since the vGPU removing hangs indefinitely). More information on the issues that this causes are described in details in this github issue post: https://github.com/intel/gvt-linux/issues/170#issuecomment-685806160 This patch solves this problem by checking is pos is equal to NULL, and if it is, it sets ret to a nagative value, making the module simply indicate that the access to EDID region has failed, without any fatal repercussion. When this patch is applied, Broadwell GPU users do not suffer from that kernel oops anymore, and thus do not encounter any of the described problems and get able to set up virtual machines with GPU passthrough without problems. Users of GPUs with proper EDID support, are of course, still able to benefit from the EDID features. Signed-off-by: Alejandro W. Sior <aho(a)sior.be> --- drivers/gpu/drm/i915/gvt/kvmgt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index ad8a9df49f29..49163363ba4a 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -557,7 +557,9 @@ static size_t intel_vgpu_reg_rw_edid(struct intel_vgpu *vgpu, char *buf, (struct vfio_edid_region *)kvmgt_vdev(vgpu)->region[i].data; loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; - if (pos < region->vfio_edid_regs.edid_offset) { + if (pos == NULL) { + ret = -EINVAL; + } else if (pos < region->vfio_edid_regs.edid_offset) { ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite); } else { pos -= EDID_BLOB_OFFSET; -- 2.28.0

1 0

[PATCH] drm/virtio: drop quirks handling
by Gerd Hoffmann 08 Sep '20

08 Sep '20

These days dma ops can be overridden per device, and the virtio core uses that to handle the dma quirks transparently for the rest of the kernel. So we can drop the virtio_has_dma_quirk() checks, just use the dma api unconditionally and depend on the virtio core having setup dma_ops as needed. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- drivers/gpu/drm/virtio/virtgpu_object.c | 19 ++++++------------- drivers/gpu/drm/virtio/virtgpu_vq.c | 16 ++++++---------- 2 files changed, 12 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c index 729f98ad7c02..9c35ce64ff9e 100644 --- a/drivers/gpu/drm/virtio/virtgpu_object.c +++ b/drivers/gpu/drm/virtio/virtgpu_object.c @@ -141,7 +141,6 @@ static int virtio_gpu_object_shmem_init(struct virtio_gpu_device *vgdev, struct virtio_gpu_mem_entry **ents, unsigned int *nents) { - bool use_dma_api = !virtio_has_dma_quirk(vgdev->vdev); struct virtio_gpu_object_shmem *shmem = to_virtio_gpu_shmem(bo); struct scatterlist *sg; int si, ret; @@ -162,15 +161,11 @@ static int virtio_gpu_object_shmem_init(struct virtio_gpu_device *vgdev, return -EINVAL; } - if (use_dma_api) { - shmem->mapped = dma_map_sg(vgdev->vdev->dev.parent, - shmem->pages->sgl, - shmem->pages->nents, - DMA_TO_DEVICE); - *nents = shmem->mapped; - } else { - *nents = shmem->pages->nents; - } + shmem->mapped = dma_map_sg(vgdev->vdev->dev.parent, + shmem->pages->sgl, + shmem->pages->nents, + DMA_TO_DEVICE); + *nents = shmem->mapped; *ents = kmalloc_array(*nents, sizeof(struct virtio_gpu_mem_entry), GFP_KERNEL); @@ -180,9 +175,7 @@ static int virtio_gpu_object_shmem_init(struct virtio_gpu_device *vgdev, } for_each_sg(shmem->pages->sgl, sg, *nents, si) { - (*ents)[si].addr = cpu_to_le64(use_dma_api - ? sg_dma_address(sg) - : sg_phys(sg)); + (*ents)[si].addr = cpu_to_le64(sg_dma_address(sg)); (*ents)[si].length = cpu_to_le32(sg->length); (*ents)[si].padding = 0; } diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c index c93c2db35aaf..1c1d2834547d 100644 --- a/drivers/gpu/drm/virtio/virtgpu_vq.c +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -599,13 +599,11 @@ void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev, struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]); struct virtio_gpu_transfer_to_host_2d *cmd_p; struct virtio_gpu_vbuffer *vbuf; - bool use_dma_api = !virtio_has_dma_quirk(vgdev->vdev); struct virtio_gpu_object_shmem *shmem = to_virtio_gpu_shmem(bo); - if (use_dma_api) - dma_sync_sg_for_device(vgdev->vdev->dev.parent, - shmem->pages->sgl, shmem->pages->nents, - DMA_TO_DEVICE); + dma_sync_sg_for_device(vgdev->vdev->dev.parent, + shmem->pages->sgl, shmem->pages->nents, + DMA_TO_DEVICE); cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); memset(cmd_p, 0, sizeof(*cmd_p)); @@ -1015,13 +1013,11 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev, struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]); struct virtio_gpu_transfer_host_3d *cmd_p; struct virtio_gpu_vbuffer *vbuf; - bool use_dma_api = !virtio_has_dma_quirk(vgdev->vdev); struct virtio_gpu_object_shmem *shmem = to_virtio_gpu_shmem(bo); - if (use_dma_api) - dma_sync_sg_for_device(vgdev->vdev->dev.parent, - shmem->pages->sgl, shmem->pages->nents, - DMA_TO_DEVICE); + dma_sync_sg_for_device(vgdev->vdev->dev.parent, + shmem->pages->sgl, shmem->pages->nents, + DMA_TO_DEVICE); cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); memset(cmd_p, 0, sizeof(*cmd_p)); -- 2.27.0

2 2

[PATCH 00/13] ttm tt refactor repost of part 1
by Dave Airlie 08 Sep '20

08 Sep '20

Most of these have r-b or acks already, patch 1 I may have posted before but found in my tree, so reposting it, and patch 5 for radeon I think were what needed re-review. I'd like to land these, and I'll revisit the remainder of this series. Dave.

4 17

[PATCH v3 0/4] drm: panel: add support for TDO tl070wsh30 panel
by Neil Armstrong 08 Sep '20

08 Sep '20

This adds support bindings and support for the TDO TL070WSH30 TFT-LCD panel module shipped with the Amlogic S400 Development Kit. The panel has a 1024×600 resolution and uses 24 bit RGB per pixel. It provides a MIPI DSI interface to the host, a built-in LED backlight and touch controller. Changes since v2 at [2]: - added reset gpio to panel-simple-dsi bindings - moved bindings to panel-simple - re-ordered prepare/unprepare - added back refresh print - moved regulator/reset handling in prepare/unprepare - aligned remove/shutdown with panel-simple - added sentinel comment into dt match table Changes since v1 at [1]: - added missing vendor-prefixes patch - removed vrefresh - fixed warning on add_panel return - removed DRM logging [1] https://patchwork.freedesktop.org/series/81376/#rev1 [2] https://patchwork.freedesktop.org/series/81376/#rev2 Neil Armstrong (4): dt-bindings: vendor-prefixes: Add Shanghai Top Display Optolelectronics vendor prefix dt-bindings: display: panel-simple-dsi: add optional reset gpio dt-bindings: display: panel-simple-dsi: add TDO TL070WSH30 DSI panel bindings drm: panel: add TDO tl070wsh30 panel driver .../display/panel/panel-simple-dsi.yaml | 3 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c | 250 ++++++++++++++++++ 5 files changed, 267 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c -- 2.22.0

2 5

[PATCH] drm/bridge: dw-mipi-dsi: fix dw_mipi_dsi_debugfs_show/write warnings
by Neil Armstrong 08 Sep '20

08 Sep '20

This fixes the following warnings while building in W=1 : dw-mipi-dsi.c:1002:5: warning: no previous prototype for 'dw_mipi_dsi_debugfs_write' [-Wmissing-prototypes] dw-mipi-dsi.c:1027:5: warning: no previous prototype for 'dw_mipi_dsi_debugfs_show' [-Wmissing-prototypes] Fixes: e2435d69204c ("drm/bridge: dw-mipi-dsi.c: Add VPG runtime config through debugfs") Reported-by: kernel test robot <lkp(a)intel.com> Cc: Angelo Ribeiro <angelo.ribeiro(a)synopsys.com> Cc: Maxime Ripard <maxime(a)cerno.tech> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Thomas Zimmermann <tzimmermann(a)suse.de> Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 0b3825a4fbdb..52f5c5a2ed64 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -999,7 +999,7 @@ static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { #ifdef CONFIG_DEBUG_FS -int dw_mipi_dsi_debugfs_write(void *data, u64 val) +static int dw_mipi_dsi_debugfs_write(void *data, u64 val) { struct debugfs_entries *vpg = data; struct dw_mipi_dsi *dsi; @@ -1024,7 +1024,7 @@ int dw_mipi_dsi_debugfs_write(void *data, u64 val) return 0; } -int dw_mipi_dsi_debugfs_show(void *data, u64 *val) +static int dw_mipi_dsi_debugfs_show(void *data, u64 *val) { struct debugfs_entries *vpg = data; -- 2.22.0

2 2

[PATCH 0/3] drm: panel: add support for TDO tl070wsh30 panel
by Neil Armstrong 08 Sep '20

08 Sep '20

This adds support bindings and support for the TDO TL070WSH30 TFT-LCD panel module shipped with the Amlogic S400 Development Kit. The panel has a 1024×600 resolution and uses 24 bit RGB per pixel. It provides a MIPI DSI interface to the host, a built-in LED backlight and touch controller. Changes since v1 at [1]: - added missing vendor-prefixes patch - removed vrefresh - fixed warning on add_panel return - removed DRM logging [1] https://patchwork.freedesktop.org/series/81376/#rev1 Neil Armstrong (3): dt-bindings: vendor-prefixes: Add Shanghai Top Display Optolelectronics vendor prefix dt-bindings: display: panel: add TDO tl070wsh30 DSI panel bindings drm: panel: add TDO tl070wsh30 panel driver .../display/panel/tdo,tl070wsh30.yaml | 58 ++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c | 256 ++++++++++++++++++ 5 files changed, 328 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/tdo,tl070wsh30.yaml create mode 100644 drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c -- 2.22.0

2 8

linux-next: build warning after merge of the drm-misc tree
by Stephen Rothwell 08 Sep '20

08 Sep '20

Hi all, After merging the drm-misc tree, today's linux-next build (x86_64 allmodconfig) produced this warning: WARNING: modpost: missing MODULE_LICENSE() in drivers/gpu/drm/panel/panel-samsung-s6e63m0.o Introduced by commit b7b23e447687 ("drm/panel: s6e63m0: Break out SPI transport") -- Cheers, Stephen Rothwell

1 0

[PATCH v5 1/2] drm/nouveau/kms/nv50-: Program notifier offset before requesting disp caps
by Lyude Paul 07 Sep '20

07 Sep '20

Not entirely sure why this never came up when I originally tested this (maybe some BIOSes already have this setup?) but the ->caps_init vfunc appears to cause the display engine to throw an exception on driver init, at least on my ThinkPad P72: nouveau 0000:01:00.0: disp: chid 0 mthd 008c data 00000000 0000508c 0000102b This is magic nvidia speak for "You need to have the DMA notifier offset programmed before you can call NV507D_GET_CAPABILITIES." So, let's fix this by doing that, and also perform an update afterwards to prevent racing with the GPU when reading capabilities. v2: * Don't just program the DMA notifier offset, make sure to actually perform an update v3: * Don't call UPDATE() * Actually read the correct notifier fields, as apparently the CAPABILITIES_DONE field lives in a different location than the main NV_DISP_CORE_NOTIFIER_1 field. As well, 907d+ use a different CAPABILITIES_DONE field then pre-907d cards. v4: * Don't forget to check the return value of core507d_read_caps() v5: * Get rid of NV50_DISP_CAPS_NTFY[14], use NV50_DISP_CORE_NTFY * Disable notifier after calling GetCapabilities() Signed-off-by: Lyude Paul <lyude(a)redhat.com> Fixes: 4a2cb4181b07 ("drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing support") Cc: <stable(a)vger.kernel.org> # v5.8+ --- drivers/gpu/drm/nouveau/dispnv50/core.h | 2 + drivers/gpu/drm/nouveau/dispnv50/core507d.c | 41 ++++++++++++++++++- drivers/gpu/drm/nouveau/dispnv50/core907d.c | 36 +++++++++++++++- drivers/gpu/drm/nouveau/dispnv50/core917d.c | 2 +- .../drm/nouveau/include/nvhw/class/cl507d.h | 5 ++- .../drm/nouveau/include/nvhw/class/cl907d.h | 4 ++ 6 files changed, 85 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core.h b/drivers/gpu/drm/nouveau/dispnv50/core.h index 498622c0c670d..f75088186fba3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core.h +++ b/drivers/gpu/drm/nouveau/dispnv50/core.h @@ -44,6 +44,7 @@ int core507d_new_(const struct nv50_core_func *, struct nouveau_drm *, s32, struct nv50_core **); int core507d_init(struct nv50_core *); void core507d_ntfy_init(struct nouveau_bo *, u32); +int core507d_read_caps(struct nv50_disp *disp); int core507d_caps_init(struct nouveau_drm *, struct nv50_disp *); int core507d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *); int core507d_update(struct nv50_core *, u32 *, bool); @@ -55,6 +56,7 @@ extern const struct nv50_outp_func pior507d; int core827d_new(struct nouveau_drm *, s32, struct nv50_core **); int core907d_new(struct nouveau_drm *, s32, struct nv50_core **); +int core907d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp); extern const struct nv50_outp_func dac907d; extern const struct nv50_outp_func sor907d; diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index 248edf69e1683..e6f16a7750f07 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -78,18 +78,55 @@ core507d_ntfy_init(struct nouveau_bo *bo, u32 offset) } int -core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) +core507d_read_caps(struct nv50_disp *disp) { struct nvif_push *push = disp->core->chan.push; int ret; - if ((ret = PUSH_WAIT(push, 2))) + ret = PUSH_WAIT(push, 6); + if (ret) return ret; + PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL, + NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) | + NVVAL(NV507D, SET_NOTIFIER_CONTROL, OFFSET, NV50_DISP_CORE_NTFY >> 2) | + NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE)); + PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000); + + PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL, + NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE)); + return PUSH_KICK(push); } +int +core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) +{ + struct nv50_core *core = disp->core; + struct nouveau_bo *bo = disp->sync; + s64 time; + int ret; + + NVBO_WR32(bo, NV50_DISP_CORE_NTFY, NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1, + NVDEF(NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1, DONE, FALSE)); + + ret = core507d_read_caps(disp); + if (ret < 0) + return ret; + + time = nvif_msec(core->chan.base.device, 2000ULL, + if (NVBO_TD32(bo, NV50_DISP_CORE_NTFY, + NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1, DONE, ==, TRUE)) + break; + usleep_range(1, 2); + ); + if (time < 0) + NV_ERROR(drm, "core caps notifier timeout\n"); + + return 0; +} + int core507d_init(struct nv50_core *core) { diff --git a/drivers/gpu/drm/nouveau/dispnv50/core907d.c b/drivers/gpu/drm/nouveau/dispnv50/core907d.c index b17c03529c784..8564d4dffaff0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core907d.c @@ -22,11 +22,45 @@ #include "core.h" #include "head.h" +#include <nvif/push507c.h> +#include <nvif/timer.h> + +#include <nvhw/class/cl907d.h> + +#include "nouveau_bo.h" + +int +core907d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) +{ + struct nv50_core *core = disp->core; + struct nouveau_bo *bo = disp->sync; + s64 time; + int ret; + + NVBO_WR32(bo, NV50_DISP_CORE_NTFY, NV907D_CORE_NOTIFIER_3, CAPABILITIES_4, + NVDEF(NV907D_CORE_NOTIFIER_3, CAPABILITIES_4, DONE, FALSE)); + + ret = core507d_read_caps(disp); + if (ret < 0) + return ret; + + time = nvif_msec(core->chan.base.device, 2000ULL, + if (NVBO_TD32(bo, NV50_DISP_CORE_NTFY, + NV907D_CORE_NOTIFIER_3, CAPABILITIES_4, DONE, ==, TRUE)) + break; + usleep_range(1, 2); + ); + if (time < 0) + NV_ERROR(drm, "core caps notifier timeout\n"); + + return 0; +} + static const struct nv50_core_func core907d = { .init = core507d_init, .ntfy_init = core507d_ntfy_init, - .caps_init = core507d_caps_init, + .caps_init = core907d_caps_init, .ntfy_wait_done = core507d_ntfy_wait_done, .update = core507d_update, .head = &head907d, diff --git a/drivers/gpu/drm/nouveau/dispnv50/core917d.c b/drivers/gpu/drm/nouveau/dispnv50/core917d.c index 66846f3720805..1cd3a2a35dfb7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core917d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core917d.c @@ -26,7 +26,7 @@ static const struct nv50_core_func core917d = { .init = core507d_init, .ntfy_init = core507d_ntfy_init, - .caps_init = core507d_caps_init, + .caps_init = core907d_caps_init, .ntfy_wait_done = core507d_ntfy_wait_done, .update = core507d_update, .head = &head917d, diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h index 2e444bac701dd..6a463f308b64f 100644 --- a/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h @@ -32,7 +32,10 @@ #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_R0 15:1 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP 29:16 - +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001 // class methods #define NV507D_UPDATE (0x00000080) diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h index 34bc3eafac7d1..79aff6ff31385 100644 --- a/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h @@ -24,6 +24,10 @@ #ifndef _cl907d_h_ #define _cl907d_h_ +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 -- 2.26.2

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Re: [PATCH v16 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables
by Caleb Connolly 07 Sep '20

07 Sep '20

On 2020-09-01 17:46, Rob Clark wrote: > From: Rob Clark <robdclark(a)chromium.org> > > NOTE: I have re-ordered the series, and propose that we could merge this > series in the following order: > > 1) 01-11 - merge via drm / msm-next > 2) 12-15 - merge via iommu, no dependency on msm-next pull req > 3) 16-18 - patch 16 has a dependency on 02 and 04, so it would > need to come post -rc1 or on following cycle, but I > think it would be unlikely to conflict with other > arm-smmu patches (other than Bjorn's smmu handover > series?) > 4) 19-20 - dt bits should be safe to land in any order without > breaking anything > > ---- > > This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware > pagetable switching. > > The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during > runtime to allow each individual instance or application to have its own > pagetable. In order to take advantage of the HW capabilities there are certain > requirements needed of the SMMU hardware. > > This series adds support for an Adreno specific arm-smmu implementation. The new > implementation 1) ensures that the GPU domain is always assigned context bank 0, > 2) enables split pagetable support (TTBR1) so that the instance specific > pagetable can be swapped while the global memory remains in place and 3) shares > the current pagetable configuration with the GPU driver to allow it to create > its own io-pgtable instances. > > The series then adds the drm/msm code to enable these features. For targets that > support it allocate new pagetables using the io-pgtable configuration shared by > the arm-smmu driver and swap them in during runtime. > > This version of the series merges the previous patchset(s) [1] and [2] > with the following improvements: > > v16: (Respin by Rob) > - Fix indentation > - Re-order series to split drm and iommu parts > v15: (Respin by Rob) > - Adjust dt bindings to keep SoC specific compatible (Doug) > - Add dts workaround for cheza fw limitation > - Add missing 'select IOMMU_IO_PGTABLE' (Guenter) > v14: (Respin by Rob) > - Minor update to 16/20 (only force ASID to zero in one place) > - Addition of sc7180 dtsi patch. > v13: (Respin by Rob) > - Switch to a private interface between adreno-smmu and GPU driver, > dropping the custom domain attr (Will Deacon) > - Rework the SCTLR.HUPCF patch to add new fields in smmu_domain->cfg > rather than adding new impl hook (Will Deacon) > - Drop for_each_cfg_sme() in favor of plain for() loop (Will Deacon) > - Fix context refcnt'ing issue which was causing problems with GPU > crash recover stress testing. > - Spiff up $debugfs/gem to show process information associated with > VMAs > v12: > - Nitpick cleanups in gpu/drm/msm/msm_iommu.c (Rob Clark) > - Reorg in gpu/drm/msm/msm_gpu.c (Rob Clark) > - Use the default asid for the context bank so that iommu_tlb_flush_all works > - Flush the UCHE after a page switch > - Add the SCTLR.HUPCF patch at the end of the series > v11: > - Add implementation specific get_attr/set_attr functions (per Rob Clark) > - Fix context bank allocation (per Bjorn Andersson) > v10: > - arm-smmu: add implementation hook to allocate context banks > - arm-smmu: Match the GPU domain by stream ID instead of compatible string > - arm-smmu: Make DOMAIN_ATTR_PGTABLE_CFG bi-directional. The leaf driver > queries the configuration to create a pagetable and then sends the newly > created configuration back to the smmu-driver to enable TTBR0 > - drm/msm: Add context reference counting for submissions > - drm/msm: Use dummy functions to skip TLB operations on per-instance > pagetables > > [1] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045653.html > [2] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045659.html > > Jordan Crouse (12): > drm/msm: Add a context pointer to the submitqueue > drm/msm: Drop context arg to gpu->submit() > drm/msm: Set the global virtual address range from the IOMMU domain > drm/msm: Add support to create a local pagetable > drm/msm: Add support for private address space instances > drm/msm/a6xx: Add support for per-instance pagetables > iommu/arm-smmu: Pass io-pgtable config to implementation specific > function > iommu/arm-smmu: Add support for split pagetables > iommu/arm-smmu: Prepare for the adreno-smmu implementation > iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU > dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU > arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU > > Rob Clark (8): > drm/msm: Remove dangling submitqueue references > drm/msm: Add private interface for adreno-smmu > drm/msm/gpu: Add dev_to_gpu() helper > drm/msm: Set adreno_smmu as gpu's drvdata > drm/msm: Show process names in gem_describe > iommu/arm-smmu: Constify some helpers > iommu/arm-smmu: Add a way for implementations to influence SCTLR > arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU > > .../devicetree/bindings/iommu/arm,smmu.yaml | 9 +- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 + > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- > drivers/gpu/drm/msm/Kconfig | 1 + > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 68 +++++- > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + > drivers/gpu/drm/msm/adreno/adreno_device.c | 12 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +- > drivers/gpu/drm/msm/msm_drv.c | 16 +- > drivers/gpu/drm/msm/msm_drv.h | 25 +++ > drivers/gpu/drm/msm/msm_gem.c | 25 ++- > drivers/gpu/drm/msm/msm_gem.h | 6 + > drivers/gpu/drm/msm/msm_gem_submit.c | 8 +- > drivers/gpu/drm/msm/msm_gem_vma.c | 10 + > drivers/gpu/drm/msm/msm_gpu.c | 41 +++- > drivers/gpu/drm/msm/msm_gpu.h | 21 +- > drivers/gpu/drm/msm/msm_gpummu.c | 2 +- > drivers/gpu/drm/msm/msm_iommu.c | 206 +++++++++++++++++- > drivers/gpu/drm/msm/msm_mmu.h | 16 +- > drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + > drivers/gpu/drm/msm/msm_submitqueue.c | 7 +- > drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 6 +- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 155 ++++++++++++- > drivers/iommu/arm/arm-smmu/arm-smmu.c | 100 ++++----- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 87 +++++++- > include/linux/adreno-smmu-priv.h | 36 +++ > 29 files changed, 771 insertions(+), 134 deletions(-) > create mode 100644 include/linux/adreno-smmu-priv.h > Tested in combination with https://lore.kernel.org/linux-arm-msm/20200904155513.282067-1-bjorn.anderss… Fixes booting on the OnePlus 6 (SDM845) with the display enabled.

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dri-devel September 2020