dri-devel October 2021

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[PATCH v14 00/39] NVIDIA Tegra power management patches for 5.17
by Dmitry Osipenko 30 Oct '21

30 Oct '21

This series adds runtime PM support to Tegra drivers and enables core voltage scaling for Tegra20/30 SoCs, resolving overheating troubles. All patches in this series are interdependent and should go via Tegra tree for simplicity. Changelog: v14: - Fixed missing runtime PM syncing on removal of drivers, which was spotted by Ulf Hansson in v13. - clk-device driver now resumes RPM on system suspend instead of preparing clock which it backs. This was suggested by Ulf Hansson. - clk-device driver now syncs power domain performance unconditionally during driver's probe time since GENPD API allows to do this now. It was spotted by Ulf Hansson. - Added new "Enable runtime PM during OPP state-syncing" patch, which allows drivers to sync state at any time. Previously drivers were obligated to take care of enabling RPM at the "right" time. - Moved runtime PM initialization/uninitialization of DRM drivers that use host1x channel to host1x client init/deinit phase. I noticed that there is UAF problem because RPM-suspend callback waits until channel is idling and channel is already released/freed during driver's removal phase. - Added system suspend support to the new NVDEC DRM driver. - Added missing pm_runtime_mark_last_busy() to DRM driver. - Corrected VDE GENPD patch which previously made video decoder clock always-enabled by mistake if legacy PD code path was used. It was spotted while we were testing VDE on Tegra114 that doesn't support GENPD yet. - Added ack from Peter Chen to the USB patch that he gave to v13. - Changed OPP table names in accordance to the new naming scheme required by the recent core OPP binding. - Added 500MHz memory OPP entry used by ASUS Transformer tablets. v13: - Fixed compile-test error reported by build bot by reverting the mmc/ patch to v11. The sdhci_suspend/resume_host() functions aren't available with the disabled CONFIG_PM_SLEEP, some code needs the ifdef. - Added last r-b from Rob Herring for the DT patches. - Corrected clk/ PM domain-support patch by not using the devm_tegra_core_dev_init_opp_table_common() helper, which I utilized in v12. The clk driver implements its own power domain state syncing and common helper shouldn't be used. This fixes driver probing for some clocks on some devices. It was reported by Svyatoslav Ryhel for PLLE OPP error on T30 Asus Transformer tablet. v12: - Added r-b from Rob Herring to the host1x binding patch. - Added acks from Hans Verkuil to the video decoder patches. - In the v11 changelog I forgot to mention that the clk-binding patch was also changed with a corrected regex pattern and removed 'clocks' sub-node. This patch needs r-b or ack too. - Added new "Rename 3d power domains" patch to match the DT schema naming requirement. Thanks to David Heidelberg for spotting this problem. - Replaced #ifdef CONFIG_PM_SLEEP with maybe_unused in the MMC patch to make code cleaner. v11: - Added acks and r-b from Rob Herring, Mark Brown and Miquel Raynal that were given to v8. - Corrected order of the new memory controller reset entry in device-trees and host1x DT binding patch, which was requested by Rob Herring. - Switched consumer drivers to use power domain state syncing done by new Tegra's common OPP-initialization helper. - Made use of new devm_pm_runtime_enable() helper that was added to v5.15 kernel, where appropriate. - Added "fuse: Use resource-managed helpers" patch. - Converted Tegra20/30 clk drivers to a proper platform drivers, which was requested by Thierry Reding. - Removed clk-bulk API usage from the MMC patch, which was requested by Thierry Reding. - Changed CORE power domain name to "core" in a new patch "Change name of core power domain". - Misc small fixes for problems that I found since v8, like couple typos in error code paths and restored working RPM for Tegra DRM UAPI v1 that was removed in v8 by accident. v9-v10: Figured out remaining GENPD API changes with Ulf Hansson and Viresh Kumar. The OPP-sync helper that was used in v8 isn't needed anymore because GENPD API now allows consumer drivers to init rpm_pstate of power domains. v8: - Added new generic dev_pm_opp_sync() helper that syncs OPP state with hardware. All drivers changed to use it. This replaces GENPD attach_dev callback hacks that were used in v7. - Added new patch patch "soc/tegra: regulators: Prepare for suspend" that fixes dying Tegra20 SoC after enabling VENC power domain during resume from suspend. It matches to what downstream kernel does on suspend/resume. - After a second thought, I dropped patches which added RPM to memory drivers since hardware is always-on and RPM not needed. - Replaced the "dummy host1x driver" patch with new "Disable unused host1x hardware" patch, since it's a cleaner solution. Dmitry Osipenko (39): soc/tegra: Enable runtime PM during OPP state-syncing soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() soc/tegra: Don't print error message when OPPs not available dt-bindings: clock: tegra-car: Document new clock sub-nodes clk: tegra: Support runtime PM and power domain dt-bindings: host1x: Document OPP and power domain properties dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D gpu: host1x: Add initial runtime PM and OPP support gpu: host1x: Add host1x_channel_stop() drm/tegra: dc: Support OPP and SoC core voltage scaling drm/tegra: hdmi: Add OPP support drm/tegra: gr2d: Support generic power domain and runtime PM drm/tegra: gr3d: Support generic power domain and runtime PM drm/tegra: vic: Stop channel on suspend drm/tegra: nvdec: Stop channel on suspend drm/tegra: submit: Remove pm_runtime_enabled() checks drm/tegra: submit: Add missing pm_runtime_mark_last_busy() usb: chipidea: tegra: Add runtime PM and OPP support bus: tegra-gmi: Add runtime PM and OPP support pwm: tegra: Add runtime PM and OPP support mmc: sdhci-tegra: Add runtime PM and OPP support mtd: rawnand: tegra: Add runtime PM and OPP support spi: tegra20-slink: Add OPP support media: dt: bindings: tegra-vde: Convert to schema media: dt: bindings: tegra-vde: Document OPP and power domain media: staging: tegra-vde: Support generic power domain soc/tegra: fuse: Reset hardware soc/tegra: fuse: Use resource-managed helpers soc/tegra: regulators: Prepare for suspend soc/tegra: pmc: Rename 3d power domains soc/tegra: pmc: Rename core power domain soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30 ARM: tegra: Rename CPU and EMC OPP table device-tree nodes ARM: tegra: Add 500MHz entry to Tegra30 memory OPP table ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x ARM: tegra20/30: Disable unused host1x hardware .../bindings/clock/nvidia,tegra20-car.yaml | 37 + .../display/tegra/nvidia,tegra20-host1x.txt | 53 + .../bindings/media/nvidia,tegra-vde.txt | 64 - .../bindings/media/nvidia,tegra-vde.yaml | 119 ++ arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 4 +- .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 4 +- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 8 +- .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 8 +- .../boot/dts/tegra124-peripherals-opp.dtsi | 140 +- .../boot/dts/tegra20-acer-a500-picasso.dts | 5 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 5 +- .../boot/dts/tegra20-cpu-opp-microvolt.dtsi | 82 +- arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 82 +- arch/arm/boot/dts/tegra20-harmony.dts | 3 +- arch/arm/boot/dts/tegra20-paz00.dts | 3 +- .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 949 +++++++++++- arch/arm/boot/dts/tegra20-seaboard.dts | 3 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 +- arch/arm/boot/dts/tegra20-trimslice.dts | 9 + arch/arm/boot/dts/tegra20-ventana.dts | 1 + arch/arm/boot/dts/tegra20.dtsi | 118 +- .../tegra30-asus-nexus7-grouper-common.dtsi | 1 + ...30-asus-nexus7-grouper-memory-timings.dtsi | 12 +- arch/arm/boot/dts/tegra30-beaver.dts | 1 + arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 17 +- .../boot/dts/tegra30-cpu-opp-microvolt.dtsi | 144 +- arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 144 +- arch/arm/boot/dts/tegra30-ouya.dts | 5 +- .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1373 ++++++++++++++++- arch/arm/boot/dts/tegra30.dtsi | 175 ++- drivers/bus/tegra-gmi.c | 53 +- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-device.c | 199 +++ drivers/clk/tegra/clk-pll.c | 2 +- drivers/clk/tegra/clk-super.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 77 +- drivers/clk/tegra/clk-tegra30.c | 116 +- drivers/clk/tegra/clk.c | 75 +- drivers/clk/tegra/clk.h | 2 + drivers/gpu/drm/tegra/dc.c | 79 + drivers/gpu/drm/tegra/dc.h | 2 + drivers/gpu/drm/tegra/gr2d.c | 184 ++- drivers/gpu/drm/tegra/gr3d.c | 363 ++++- drivers/gpu/drm/tegra/hdmi.c | 16 +- drivers/gpu/drm/tegra/nvdec.c | 29 +- drivers/gpu/drm/tegra/submit.c | 14 +- drivers/gpu/drm/tegra/vic.c | 36 +- drivers/gpu/host1x/channel.c | 8 + drivers/gpu/host1x/debug.c | 15 + drivers/gpu/host1x/dev.c | 150 +- drivers/gpu/host1x/dev.h | 3 +- drivers/gpu/host1x/hw/channel_hw.c | 44 +- drivers/gpu/host1x/intr.c | 3 - drivers/gpu/host1x/syncpt.c | 5 +- drivers/mmc/host/sdhci-tegra.c | 81 +- drivers/mtd/nand/raw/tegra_nand.c | 60 +- drivers/pwm/pwm-tegra.c | 84 +- drivers/soc/tegra/common.c | 20 +- drivers/soc/tegra/fuse/fuse-tegra.c | 51 +- drivers/soc/tegra/fuse/fuse-tegra20.c | 33 +- drivers/soc/tegra/fuse/fuse.h | 1 + drivers/soc/tegra/pmc.c | 14 +- drivers/soc/tegra/regulators-tegra20.c | 99 ++ drivers/soc/tegra/regulators-tegra30.c | 122 ++ drivers/spi/spi-tegra20-slink.c | 9 +- drivers/staging/media/tegra-vde/vde.c | 63 +- drivers/usb/chipidea/ci_hdrc_tegra.c | 55 +- include/linux/host1x.h | 1 + include/soc/tegra/common.h | 15 + 70 files changed, 4936 insertions(+), 823 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml create mode 100644 drivers/clk/tegra/clk-device.c -- 2.33.1

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[PATCH 1/3] drm/bridge: parade-ps8640: Don't try to enable VDO if poweron fails
by AngeloGioacchino Del Regno 30 Oct '21

30 Oct '21

If the bridge cannot get powered on, there's no reason to try to communicate with it: change the ps8640_bridge_poweron function to return an error value to the caller, so that we can avoid calling ps8640_bridge_vdo_control() in ps8640_pre_enable() if the poweron sequence fails. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno(a)collabora.com> --- drivers/gpu/drm/bridge/parade-ps8640.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 4b36e4dc78f1..8c5402947b3c 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -293,19 +293,19 @@ static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, return 0; } -static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) +static int ps8640_bridge_poweron(struct ps8640 *ps_bridge) { struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; int ret, status; if (ps_bridge->powered) - return; + return 0; ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), ps_bridge->supplies); if (ret < 0) { DRM_ERROR("cannot enable regulators %d\n", ret); - return; + return ret; } gpiod_set_value(ps_bridge->gpio_powerdown, 0); @@ -352,11 +352,13 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) ps_bridge->powered = true; - return; + return 0; err_regulators_disable: regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), ps_bridge->supplies); + + return ret; } static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge) @@ -381,7 +383,9 @@ static void ps8640_pre_enable(struct drm_bridge *bridge) struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); int ret; - ps8640_bridge_poweron(ps_bridge); + ret = ps8640_bridge_poweron(ps_bridge); + if (ret) + return; ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE); if (ret < 0) -- 2.33.0

2 4

[PATCH 1/2] drm/i915/pmu: Add a name to the execlists stats
by Umesh Nerlige Ramappa 30 Oct '21

30 Oct '21

In preparation for GuC pmu stats, add a name to the execlists stats structure so that it can be differentiated from the GuC stats. Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 +++--- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33 +++++++------ drivers/gpu/drm/i915/gt/intel_engine_types.h | 52 +++++++++++--------- 3 files changed, 53 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index ff6753ccb129..2de396e34d83 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -363,7 +363,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, DRIVER_CAPS(i915)->has_logical_contexts = true; ewma__engine_latency_init(&engine->latency); - seqcount_init(&engine->stats.lock); + seqcount_init(&engine->stats.execlists.lock); ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); @@ -1918,15 +1918,16 @@ void intel_engine_dump(struct intel_engine_cs *engine, static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) { - ktime_t total = engine->stats.total; + struct intel_engine_execlists_stats *stats = &engine->stats.execlists; + ktime_t total = stats->total; /* * If the engine is executing something at the moment * add it to the total. */ *now = ktime_get(); - if (READ_ONCE(engine->stats.active)) - total = ktime_add(total, ktime_sub(*now, engine->stats.start)); + if (READ_ONCE(stats->active)) + total = ktime_add(total, ktime_sub(*now, stats->start)); return total; } @@ -1940,13 +1941,14 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, */ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) { + struct intel_engine_execlists_stats *stats = &engine->stats.execlists; unsigned int seq; ktime_t total; do { - seq = read_seqcount_begin(&engine->stats.lock); + seq = read_seqcount_begin(&stats->lock); total = __intel_engine_get_busy_time(engine, now); - } while (read_seqcount_retry(&engine->stats.lock, seq)); + } while (read_seqcount_retry(&stats->lock, seq)); return total; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h index 24fbdd94351a..8e762d683e50 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_stats.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -15,45 +15,46 @@ static inline void intel_engine_context_in(struct intel_engine_cs *engine) { + struct intel_engine_execlists_stats *stats = &engine->stats.execlists; unsigned long flags; - if (engine->stats.active) { - engine->stats.active++; + if (stats->active) { + stats->active++; return; } /* The writer is serialised; but the pmu reader may be from hardirq */ local_irq_save(flags); - write_seqcount_begin(&engine->stats.lock); + write_seqcount_begin(&stats->lock); - engine->stats.start = ktime_get(); - engine->stats.active++; + stats->start = ktime_get(); + stats->active++; - write_seqcount_end(&engine->stats.lock); + write_seqcount_end(&stats->lock); local_irq_restore(flags); - GEM_BUG_ON(!engine->stats.active); + GEM_BUG_ON(!stats->active); } static inline void intel_engine_context_out(struct intel_engine_cs *engine) { + struct intel_engine_execlists_stats *stats = &engine->stats.execlists; unsigned long flags; - GEM_BUG_ON(!engine->stats.active); - if (engine->stats.active > 1) { - engine->stats.active--; + GEM_BUG_ON(!stats->active); + if (stats->active > 1) { + stats->active--; return; } local_irq_save(flags); - write_seqcount_begin(&engine->stats.lock); + write_seqcount_begin(&stats->lock); - engine->stats.active--; - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); + stats->active--; + stats->total = ktime_add(stats->total, + ktime_sub(ktime_get(), stats->start)); - write_seqcount_end(&engine->stats.lock); + write_seqcount_end(&stats->lock); local_irq_restore(flags); } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index e0f773585c29..24fa7fb0e7de 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -257,6 +257,33 @@ struct intel_engine_execlists { #define INTEL_ENGINE_CS_MAX_NAME 8 +struct intel_engine_execlists_stats { + /** + * @active: Number of contexts currently scheduled in. + */ + unsigned int active; + + /** + * @lock: Lock protecting the below fields. + */ + seqcount_t lock; + + /** + * @total: Total time this engine was busy. + * + * Accumulated time not counting the most recent block in cases where + * engine is currently busy (active > 0). + */ + ktime_t total; + + /** + * @start: Timestamp of the last idle to active transition. + * + * Idle is defined as active == 0, active is active > 0. + */ + ktime_t start; +}; + struct intel_engine_cs { struct drm_i915_private *i915; struct intel_gt *gt; @@ -488,30 +515,7 @@ struct intel_engine_cs { u32 (*get_cmd_length_mask)(u32 cmd_header); struct { - /** - * @active: Number of contexts currently scheduled in. - */ - unsigned int active; - - /** - * @lock: Lock protecting the below fields. - */ - seqcount_t lock; - - /** - * @total: Total time this engine was busy. - * - * Accumulated time not counting the most recent block in cases - * where engine is currently busy (active > 0). - */ - ktime_t total; - - /** - * @start: Timestamp of the last idle to active transition. - * - * Idle is defined as active == 0, active is active > 0. - */ - ktime_t start; + struct intel_engine_execlists_stats execlists; /** * @rps: Utilisation at last RPS sampling. -- 2.20.1

2 4

[PATCH] drm/bridge: analogix_dp: Make PSR-disable non-blocking
by Brian Norris 29 Oct '21

29 Oct '21

Prior to commit 6c836d965bad ("drm/rockchip: Use the helpers for PSR"), "PSR disable" used non-blocking analogix_dp_send_psr_spd(). The refactor accidentally (?) set blocking=true. This can cause upwards of 60-100ms of unneeded latency when exiting self-refresh, which can cause very noticeable lag when, say, moving a cursor. Presumbaly it's OK to let the display finish exiting refresh in parallel with clocking out the next video frames, so we shouldn't hold up the atomic_enable() step. This also brings behavior in line with the downstream ("mainline-derived") variant of the driver currently deployed to Chrome OS Rockchip systems. Tested on a Samsung Chromebook Plus (i.e., Rockchip RK3399 Gru Kevin). Fixes: 6c836d965bad ("drm/rockchip: Use the helpers for PSR") Cc: <stable(a)vger.kernel.org> Cc: Zain Wang <wzz(a)rock-chips.com> Cc: Tomasz Figa <tfiga(a)chromium.org> Cc: Heiko Stuebner <heiko(a)sntech.de> Cc: Sean Paul <seanpaul(a)chromium.org> Signed-off-by: Brian Norris <briannorris(a)chromium.org> --- CC list is partially constructed from the commit message of the Fixed commit drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index b7d2e4449cfa..fbe6eb9df310 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1055,7 +1055,7 @@ static int analogix_dp_disable_psr(struct analogix_dp_device *dp) psr_vsc.db[0] = 0; psr_vsc.db[1] = 0; - return analogix_dp_send_psr_spd(dp, &psr_vsc, true); + return analogix_dp_send_psr_spd(dp, &psr_vsc, false); } /* -- 2.33.0.1079.g6e70778dc9-goog

2 4

[RESEND PATCH v3 0/6] drm/ingenic: Various improvements v3
by Paul Cercueil 29 Oct '21

29 Oct '21

Hi, I resend the V3 of my patchset for drm/ingenic, verbatim. The previous submission of my V3 received a lot of replies, but none of these replies were actually talking about the patches themselves. Cheers, -Paul Paul Cercueil (6): drm/ingenic: Simplify code by using hwdescs array drm/ingenic: Add support for private objects drm/ingenic: Move IPU scale settings to private state drm/ingenic: Set DMA descriptor chain register when starting CRTC drm/ingenic: Upload palette before frame drm/ingenic: Attach bridge chain to encoders drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 278 +++++++++++++++++----- drivers/gpu/drm/ingenic/ingenic-ipu.c | 127 ++++++++-- 2 files changed, 333 insertions(+), 72 deletions(-) -- 2.33.0

4 15

[v2] drm/msm/disp/dpu1: set default group ID for CTL.
by Kalyan Thota 29 Oct '21

29 Oct '21

New required programming in CTL for SC7280. Group ID informs HW of which VM owns that CTL. Force this group ID to default/disabled until virtualization support is enabled in SW. Changes in v1: - Fix documentation and add descritpion for the change (Stephen) Signed-off-by: Kalyan Thota <quic_kalyant(a)quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 8 ++++++++ 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ce6f32a..283605c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -45,7 +45,7 @@ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE)) + (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG)) #define MERGE_3D_SM8150_MASK (0) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4ade44b..31af04a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -179,13 +179,16 @@ enum { /** * CTL sub-blocks - * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display + * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display + * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) + * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_MAX */ enum { DPU_CTL_SPLIT_DISPLAY = 0x1, DPU_CTL_ACTIVE_CFG, DPU_CTL_FETCH_ACTIVE, + DPU_CTL_VM_CFG, DPU_CTL_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 64740ddb..02da9ec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -36,6 +36,7 @@ #define MERGE_3D_IDX 23 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff +#define CTL_DEFAULT_GROUP_ID 0xf static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0, @@ -498,6 +499,13 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 mode_sel = 0; + /* CTL_TOP[31:28] carries group_id to collate CTL paths + * per VM. Explicitly disable it until VM support is + * added in SW. Power on reset value is not disable. + */ + if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features))) + mode_sel = CTL_DEFAULT_GROUP_ID << 28; + if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD) mode_sel |= BIT(17); -- 2.7.4

3 2

[pull] amdgpu, amdkfd drm-next-5.16
by Alex Deucher 29 Oct '21

29 Oct '21

Hi Dave, Daniel, Fixes for 5.16. The following changes since commit 31fa8cbce4664946a1688898410fee41ad05364d: drm: Add R10 and R12 FourCC (2021-10-28 17:20:45 +1000) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.16-2021-10-29 for you to fetch changes up to 403475be6d8b122c3e6b8a47e075926d7299e5ef: drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bits (2021-10-28 14:27:00 -0400) ---------------------------------------------------------------- amd-drm-next-5.16-2021-10-29: amdgpu: - RAS fixes - Fix a potential memory leak in device tear down - Add a stutter mode quirk - Misc display fixes - Further display FP refactoring - Display USB4 fixes - Display DP2.0 fixes - DCN 3.1 fixes - Display 8 ch audio fix - Fix DMA mask regression for SI parts - Aldebaran fixes amdkfd: - userptr fix - BO lifetime fix - Misc code cleanup UAPI: - Minor header cleanup (no functional change) ---------------------------------------------------------------- Ahmad Othman (2): drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1 drm/amd/display: fix a crash on USB4 over C20 PHY Alex Deucher (6): drm/amdgpu/display: add quirk handling for stutter mode drm/amdgpu/pm: look up current_level for asics without pm callback drm/amdgpu/UAPI: rearrange header to better align related items drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 parts drm/amdgpu/discovery: add SDMA IP instance info for soc15 parts drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bits Anson Jacob (2): drm/amd/display: dcn20_resource_construct reduce scope of FPU enabled drm/amd/display: Remove unused macros Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.89 drm/amd/display: [FW Promotion] Release 0.0.90 Aric Cyr (4): drm/amd/display: Handle I2C-over-AUX write channel status update drm/amd/display: 3.2.158 drm/amd/display: Fix 3DLUT skipped programming drm/amd/display: 3.2.159 Candice Li (1): drm/amdgpu: Update TA version output in driver Dmytro Laktyushkin (3): drm/amd/display: clean up dcn31 revision check drm/amd/display: restyle dcn31 resource header inline with other asics drm/amd/display: allow windowed mpo + odm George Shen (2): drm/amd/display: Implement fixed DP drive settings drm/amd/display: Add comment for preferred_training_settings Guo, Bing (2): drm/amd/display: Get ceiling for v_total calc drm/amd/display: set Layout properly for 8ch audio at timing validation Hansen (1): drm/amd/display: Set phy_mux_sel bit in dmub scratch register Jimmy Kizito (1): drm/amd/display: Add workaround flag for EDID read on certain docks Jude Shih (2): drm/amd/display: Fix USB4 hot plug crash issue drm/amd/display: Enable dpia in dmub only for DCN31 B0 Kent Russell (2): drm/amdgpu: Warn when bad pages approaches 90% threshold drm/amdgpu: Add kernel parameter support for ignoring bad page threshold Lang Yu (4): drm/amdkfd: Separate pinned BOs destruction from general routine drm/amdgpu: fix a potential memory leak in amdgpu_device_fini_sw() drm/amdkfd: Add an optional argument into update queue operation(v2) drm/amdkfd: Remove cu mask from struct queue_properties(v2) Lewis Huang (1): drm/amd/display: Align bw context with hw config when system resume Martin Leung (1): drm/amd/display: Manually adjust strobe for DCN303 Meenakshikumar Somasundaram (3): drm/amd/display: FEC configuration for dpia links drm/amd/display: FEC configuration for dpia links in MST mode drm/amd/display: MST support for DPIA Michael Strauss (3): drm/amd/display: Set i2c memory to light sleep during hw init drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdate drm/amd/display: Fallback to clocks which meet requested voltage on DCN31 Nicholas Kazlauskas (1): drm/amd/display: Fix deadlock when falling back to v2 from v3 Patrik Jakobsson (1): drm/amdgpu: Fix even more out of bound writes from debugfs Philip Yang (1): drm/amdkfd: restore userptr ignore bad address error Qingqing Zhuo (2): drm/amd/display: move FPU associated DSC code to DML folder drm/amd/display: move FPU associated DCN301 code to DML folder Robin Chen (1): drm/amd/display: dc_link_set_psr_allow_active refactoring Tao Zhou (2): drm/amdgpu: skip GPRs init for some CU settings on ALDEBARAN drm/amdgpu: remove GPRs init for ALDEBARAN in gpu reset (v3) Wenjing Liu (5): drm/amd/display: adopt DP2.0 LT SCR revision 8 drm/amd/display: implement decide lane settings drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings drm/amd/display: add two lane settings training options drm/amd/display: fix link training regression for 1 or 2 lane drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 37 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 17 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 22 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 5 + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8 +- drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 4 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 62 ++- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 +- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 32 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 19 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 19 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 35 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 26 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 109 +++-- .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 24 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 72 ++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 18 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 10 +- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 + drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 16 +- .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 13 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 71 ++- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 146 +++++- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 15 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 498 +++++++++------------ drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c | 57 ++- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 +- drivers/gpu/drm/amd/display/dc/dc.h | 29 +- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 5 - drivers/gpu/drm/amd/display/dc/dc_link.h | 13 +- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 6 +- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 34 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 3 +- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 20 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 1 + .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 12 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 + .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 19 +- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 14 + .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c | 8 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 35 +- drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 26 -- .../drm/amd/display/dc/dcn301/dcn301_resource.c | 349 +-------------- .../drm/amd/display/dc/dcn301/dcn301_resource.h | 3 + .../drm/amd/display/dc/dcn303/dcn303_resource.c | 14 + .../amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 4 +- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 5 + .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 11 +- .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.h | 10 + drivers/gpu/drm/amd/display/dc/dm_cp_psp.h | 2 + drivers/gpu/drm/amd/display/dc/dml/Makefile | 6 + .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 390 ++++++++++++++++ .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h | 42 ++ .../drm/amd/display/dc/{ => dml}/dsc/qp_tables.h | 0 .../gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 291 ++++++++++++ .../gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h | 94 ++++ drivers/gpu/drm/amd/display/dc/dsc/Makefile | 29 -- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 259 ----------- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 50 +-- drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 1 - drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 16 +- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 82 +++- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 3 + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 1 + .../amd/display/include/grph_object_ctrl_defs.h | 1 + .../gpu/drm/amd/display/include/i2caux_interface.h | 3 + .../drm/amd/display/include/link_service_types.h | 29 +- .../drm/amd/display/modules/freesync/freesync.c | 15 +- .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 6 +- drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 2 + drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 +- include/uapi/drm/amdgpu_drm.h | 13 +- 89 files changed, 2054 insertions(+), 1334 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h rename drivers/gpu/drm/amd/display/dc/{ => dml}/dsc/qp_tables.h (100%) create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h

1 0

[PULL] topic/amdgpu-dp2.0-mst
by Lyude Paul 29 Oct '21

29 Oct '21

topic/amdgpu-dp2.0-mst-2021-10-27: UAPI Changes: Nope! Cross-subsystem Changes: drm_dp_update_payload_part1() takes a new argument for specifying what the VCPI slot start is Core Changes: Make the DP MST helpers aware of the current starting VCPI slot/VCPI total slot count... Driver Changes: ...and then add support for taking advantage of this for 128b/132b links on DP 2.0 for amdgpu The following changes since commit 6f2f7c83303d2227f47551423e507d77d9ea01c7: Merge tag 'drm-intel-gt-next-2021-10-21' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-10-22 06:30:34 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/topic/amdgpu-dp2.0-mst-2021- 10-27 for you to fetch changes up to 00f965e700ef5aa2d889e7e65c7458531d2a4bcf: drm/amdgpu/display: fix build when CONFIG_DRM_AMD_DC_DCN is not set (2021- 10-27 19:50:26 -0400) ---------------------------------------------------------------- UAPI Changes: Nope! Cross-subsystem Changes: drm_dp_update_payload_part1() takes a new argument for specifying what the VCPI slot start is Core Changes: Make the DP MST helpers aware of the current starting VCPI slot/VCPI total slot count... Driver Changes: ...and then add support for taking advantage of this for 128b/132b links on DP 2.0 for amdgpu ---------------------------------------------------------------- Alex Deucher (1): drm/amdgpu/display: fix build when CONFIG_DRM_AMD_DC_DCN is not set Bhawanpreet Lakha (3): drm: Remove slot checks in dp mst topology during commit drm: Update MST First Link Slot Information Based on Encoding Format drm/amd/display: Add DP 2.0 MST DM Support Fangzhi Zuo (1): drm/amd/display: Add DP 2.0 MST DC Support drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 ++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 7 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 292 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 19 ++ drivers/gpu/drm/amd/display/dc/dc_link.h | 7 + drivers/gpu/drm/amd/display/dc/dc_stream.h | 13 + drivers/gpu/drm/drm_dp_mst_topology.c | 42 ++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +- drivers/gpu/drm/radeon/radeon_dp_mst.c | 4 +- include/drm/drm_dp_mst_helper.h | 5 +- 13 files changed, 425 insertions(+), 16 deletions(-) -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat

2 3

[PATCH v3 0/6] Add support for eDP controller on SC7280
by Sankeerth Billakanti 29 Oct '21

29 Oct '21

This series will add eDP controller support for Qualcomm SC7280 platform. These patches are baseline changes with which we can enable eDP display on sc7280. The sc7280 eDP controller driver can also support additional features such as no_hpd detection, PSR, etc. which will be enabled in subsequent patch series. This is based on Bjorn's changes in the below mentioned series to support both eDP and DP programming through the same driver: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=564841 Sankeerth Billakanti (6): dt-bindings: msm/dp: Add DP compatible strings for sc7280 drm/msm/dp: Add DP controllers for sc7280 drm/dp: Add macro to check max_downspread capability drm/msm/dp: Enable downspread for supported DP sinks drm/msm/dp: Enable ASSR for supported DP sinks drm/msm/dp: Remove the hpd init delay for eDP .../bindings/display/msm/dp-controller.yaml | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- drivers/gpu/drm/msm/dp/dp_ctrl.c | 23 +++++++++++++++++++--- drivers/gpu/drm/msm/dp/dp_display.c | 20 ++++++++++++++++++- include/drm/drm_dp_helper.h | 6 ++++++ 5 files changed, 49 insertions(+), 6 deletions(-) -- 2.7.4

3 13

[PATCH] drm/bridge: Fix the bridge chain order for pre_enable / post_disable
by Douglas Anderson 29 Oct '21

29 Oct '21

Right now, the chaining order of pre_enable/enable/disable/post_disable looks like this: pre_enable: start from connector and move to encoder enable: start from encoder and move to connector disable: start from connector and move to encoder post_disable: start from encoder and move to connector In the above, it can be seen that at least pre_enable() and post_disable() are opposites of each other and enable() and disable() are opposites. However, it seems broken that pre_enable() and enable() would not move in the same direction. In other parts of Linux you can see that various stages move in the same order. For instance, during system suspend the "early" calls run in the same order as the normal calls run in the same order as the "late" calls run in the same order as the "noirq" calls. Let fix the above so that it makes more sense. Now we'll have: pre_enable: start from encoder and move to connector enable: start from encoder and move to connector disable: start from connector and move to encoder post_disable: start from connector and move to encoder This order is chosen because if there are parent-child relationships anywhere I would expect that the encoder would be a parent and the connector a child--not the other way around. This can be important when using the DP AUX bus to instantiate a panel. The DP AUX bus is likely part of a bridge driver and is a parent of the panel. We'd like the bridge to be pre_enabled before the panel and the panel to be post_disabled before the bridge. Specifically, this allows pm_runtime_put_sync_suspend() in a bridge driver's post_suspend to work properly even a panel is under it. NOTE: it's entirely possible that this change could break someone who was relying on the old order. Hopefully this isn't the case, but if this does break someone it seems like it's better to do it sonner rather than later so we can fix everyone to handle the order that makes the most sense. A FURTHER NOTE: Looking closer at commit 4e5763f03e10 ("drm/bridge: ti-sn65dsi86: Wrap panel with panel-bridge") you can see that patch inadvertently changed the order of things. The order used to be correct (panel prepare was at the tail of the bridge enable) but it became backwards. We'll restore the original order with this patch. Fixes: 4e5763f03e10 ("drm/bridge: ti-sn65dsi86: Wrap panel with panel-bridge") Fixes: 05193dc38197 ("drm/bridge: Make the bridge chain a double-linked list") Signed-off-by: Douglas Anderson <dianders(a)chromium.org> --- drivers/gpu/drm/drm_bridge.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index c96847fc0ebc..98808af59afd 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -583,18 +583,14 @@ EXPORT_SYMBOL(drm_bridge_chain_mode_set); void drm_bridge_chain_pre_enable(struct drm_bridge *bridge) { struct drm_encoder *encoder; - struct drm_bridge *iter; if (!bridge) return; encoder = bridge->encoder; - list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { - if (iter->funcs->pre_enable) - iter->funcs->pre_enable(iter); - - if (iter == bridge) - break; + list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { + if (bridge->funcs->pre_enable) + bridge->funcs->pre_enable(bridge); } } EXPORT_SYMBOL(drm_bridge_chain_pre_enable); @@ -684,26 +680,30 @@ void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge, struct drm_atomic_state *old_state) { struct drm_encoder *encoder; + struct drm_bridge *iter; if (!bridge) return; encoder = bridge->encoder; - list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { - if (bridge->funcs->atomic_post_disable) { + list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { + if (iter->funcs->atomic_post_disable) { struct drm_bridge_state *old_bridge_state; old_bridge_state = drm_atomic_get_old_bridge_state(old_state, - bridge); + iter); if (WARN_ON(!old_bridge_state)) return; - bridge->funcs->atomic_post_disable(bridge, - old_bridge_state); - } else if (bridge->funcs->post_disable) { - bridge->funcs->post_disable(bridge); + iter->funcs->atomic_post_disable(iter, + old_bridge_state); + } else if (iter->funcs->post_disable) { + iter->funcs->post_disable(iter); } + + if (iter == bridge) + break; } } EXPORT_SYMBOL(drm_atomic_bridge_chain_post_disable); -- 2.33.0.1079.g6e70778dc9-goog

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dri-devel October 2021