dri-devel October 2021

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[PATCH] [RFC] dt-bindings: display: bridge: sil, sii9022: Convert to json-schema
by Geert Uytterhoeven 29 Oct '21

29 Oct '21

Convert the Silicon Image sii902x HDMI bridge Device Tree binding documentation to json-schema. Add missing sil,sii9022-cpi and sil,sii9022-tpi compatible values. Signed-off-by: Geert Uytterhoeven <geert+renesas(a)glider.be> --- RFC as I do not know the meaning of the various ports subnodes. --- .../bindings/display/bridge/sii902x.txt | 78 ---------- .../bindings/display/bridge/sil,sii9022.yaml | 133 ++++++++++++++++++ 2 files changed, 133 insertions(+), 78 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/sii902x.txt create mode 100644 Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/sii902x.txt b/Documentation/devicetree/bindings/display/bridge/sii902x.txt deleted file mode 100644 index 3bc760cc31cbbeee..0000000000000000 --- a/Documentation/devicetree/bindings/display/bridge/sii902x.txt +++ /dev/null @@ -1,78 +0,0 @@ -sii902x HDMI bridge bindings - -Required properties: - - compatible: "sil,sii9022" - - reg: i2c address of the bridge - -Optional properties: - - interrupts: describe the interrupt line used to inform the host - about hotplug events. - - reset-gpios: OF device-tree gpio specification for RST_N pin. - - iovcc-supply: I/O Supply Voltage (1.8V or 3.3V) - - cvcc12-supply: Digital Core Supply Voltage (1.2V) - - HDMI audio properties: - - #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin - is wired, <1> if the both are wired. HDMI audio is - configured only if this property is found. - - sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3 - Each integer indicates which i2s pin is connected to which - audio fifo. The first integer selects i2s audio pin for the - first audio fifo#0 (HDMI channels 1&2), second for fifo#1 - (HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s - pins (SD0 - SD3). Any i2s pin can be connected to any fifo, - but there can be no gaps. E.g. an i2s pin must be mapped to - fifo#0 and fifo#1 before mapping a channel to fifo#2. Default - value is <0>, describing SD0 pin beiging routed to hdmi audio - fifo #0. - - clocks: phandle and clock specifier for each clock listed in - the clock-names property - - clock-names: "mclk" - Describes SII902x MCLK input. MCLK can be used to produce - HDMI audio CTS values. This property follows - Documentation/devicetree/bindings/clock/clock-bindings.txt - consumer binding. - - If HDMI audio is configured the sii902x device becomes an I2S - and/or spdif audio codec component (e.g a digital audio sink), - that can be used in configuring a full audio devices with - simple-card or audio-graph-card binding. See their binding - documents on how to describe the way the sii902x device is - connected to the rest of the audio system: - Documentation/devicetree/bindings/sound/simple-card.yaml - Documentation/devicetree/bindings/sound/audio-graph-card.yaml - Note: In case of the audio-graph-card binding the used port - index should be 3. - -Optional subnodes: - - video input: this subnode can contain a video input port node - to connect the bridge to a display controller output (See this - documentation [1]). - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - hdmi-bridge@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - reset-gpios = <&pioA 1 0>; - iovcc-supply = <&v3v3_hdmi>; - cvcc12-supply = <&v1v2_hdmi>; - - #sound-dai-cells = <0>; - sil,i2s-data-lanes = < 0 1 2 >; - clocks = <&mclk>; - clock-names = "mclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - bridge_in: endpoint { - remote-endpoint = <&dc_out>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml b/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml new file mode 100644 index 0000000000000000..4e5a8ecf87647e8b --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/sil,sii9022.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Image sii902x HDMI bridge + +maintainers: + - Boris Brezillon <bbrezillon(a)kernel.org> + +properties: + compatible: + oneOf: + - items: + - enum: + - sil,sii9022-cpi + - sil,sii9022-tpi + - const: sil,sii9022 + - const: sil,sii9022 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: Interrupt line used to inform the host about hotplug events. + + reset-gpios: + maxItems: 1 + + iovcc-supply: + description: I/O Supply Voltage (1.8V or 3.3V) + + cvcc12-supply: + description: Digital Core Supply Voltage (1.2V) + + '#sound-dai-cells': + enum: [ 0, 1 ] + description: | + <0> if only i2s or spdif pin is wired, + <1> if both are wired. + HDMI audio is configured only if this property is found. + If HDMI audio is configured the sii902x device becomes an I2S and/or + spdif audio codec component (e.g. a digital audio sink), that can be used + in configuring a full audio devices with simple-card or audio-graph-card + binding. See their binding documents on how to describe the way the + sii902x device is connected to the rest of the audio system: + Documentation/devicetree/bindings/sound/simple-card.yaml + Documentation/devicetree/bindings/sound/audio-graph-card.yaml + Note: In case of the audio-graph-card binding the used port index should + be 3. + + sil,i2s-data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + items: + - enum: [ 0, 1, 2, 3 ] + - enum: [ 0, 1, 2, 3 ] + - enum: [ 0, 1, 2, 3 ] + - enum: [ 0, 1, 2, 3 ] + description: + Each integer indicates which i2s pin is connected to which audio fifo. + The first integer selects i2s audio pin for the first audio fifo#0 (HDMI + channels 1&2), second for fifo#1 (HDMI channels 3&4), and so on. There + are 4 fifos and 4 i2s pins (SD0 - SD3). Any i2s pin can be connected to + any fifo, but there can be no gaps. E.g. an i2s pin must be mapped to + fifo#0 and fifo#1 before mapping a channel to fifo#2. Default value is + <0>, describing SD0 pin being routed to hdmi audio fifo #0. + + clocks: + maxItems: 1 + description: MCLK input. MCLK can be used to produce HDMI audio CTS values. + + clock-names: + const: mclk + + ports: + type: object + properties: + port@0: + type: object + description: FIXME + + port@1: + type: object + description: FIXME + + port@2: + type: object + description: FIXME + + port@3: + type: object + description: FIXME + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hdmi-bridge@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + reset-gpios = <&pioA 1 0>; + iovcc-supply = <&v3v3_hdmi>; + cvcc12-supply = <&v1v2_hdmi>; + + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 1 2 >; + clocks = <&mclk>; + clock-names = "mclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dc_out>; + }; + }; + }; + }; + }; -- 2.25.1

2 1

[PATCH 00/11] i915: Initial multi-tile support
by Matt Roper 29 Oct '21

29 Oct '21

Some of our upcoming platforms, including the Xe_HP SDV, support a "multi-tile" design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but further work (especially related to local memory) will be required to fully enable a multi-tile platform. Note that the presence of multiple GTs is largely transparent to userspace. A multi-tile platform will advertise a larger list of engines to userspace, but the concept of "tile" is not something userspace has to worry about directly. There will be some uapi implications later due to the devices having multiple local memory regions, but that aspect of multi-tile is not covered by this patch series and will show up in future work. Daniele Ceraolo Spurio (2): drm/i915: split general MMIO setup from per-GT uncore init drm/i915: Initial support for per-tile uncore Matt Roper (1): drm/i915: Restructure probe to handle multi-tile platforms Michal Wajdeczko (1): drm/i915/guc: Update CT debug macro for multi-tile Michał Winiarski (1): drm/i915: Store backpointer to GT in uncore Paulo Zanoni (3): drm/i915: rework some irq functions to take intel_gt as argument drm/i915/xehp: Determine which tile raised an interrupt drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Tvrtko Ursulin (2): drm/i915: Prepare for multiple gts drm/i915/xehpsdv: Initialize multi-tiles Venkata Sandeep Dhanalakota (1): drm/i915: Release per-gt resources allocated drivers/gpu/drm/i915/gt/intel_gt.c | 180 +++++++++++++++++- drivers/gpu/drm/i915/gt/intel_gt.h | 11 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +- drivers/gpu/drm/i915/i915_debugfs.c | 5 +- drivers/gpu/drm/i915/i915_drv.c | 80 ++++++-- drivers/gpu/drm/i915/i915_drv.h | 9 + drivers/gpu/drm/i915/i915_irq.c | 71 ++++--- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_memory_region.h | 3 + drivers/gpu/drm/i915/intel_uncore.c | 36 ++-- drivers/gpu/drm/i915/intel_uncore.h | 6 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +- 17 files changed, 345 insertions(+), 89 deletions(-) -- 2.33.0

6 31

[PATCH] drm/i915/resets: Don't set / test for per-engine reset bits with GuC submission
by Matthew Brost 28 Oct '21

28 Oct '21

Don't set, test for, or clear per-engine reset bits with GuC submission as the GuC owns the per engine resets not the i915. Setting, testing for, and clearing these bits is causing issues with the hangcheck selftest. Rather than change to test to not use these bits, rip the use of these bits out from the reset code. Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_reset.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 91200c43951f..51b56b8e5003 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -1367,20 +1367,27 @@ void intel_gt_handle_error(struct intel_gt *gt, /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */ synchronize_rcu_expedited(); - /* Prevent any other reset-engine attempt. */ - for_each_engine(engine, gt, tmp) { - while (test_and_set_bit(I915_RESET_ENGINE + engine->id, - &gt->reset.flags)) - wait_on_bit(&gt->reset.flags, - I915_RESET_ENGINE + engine->id, - TASK_UNINTERRUPTIBLE); + /* + * Prevent any other reset-engine attempt. We don't do this for GuC + * submission the GuC owns the per-engine reset, not the i915. + */ + if (!intel_uc_uses_guc_submission(&gt->uc)) { + for_each_engine(engine, gt, tmp) { + while (test_and_set_bit(I915_RESET_ENGINE + engine->id, + &gt->reset.flags)) + wait_on_bit(&gt->reset.flags, + I915_RESET_ENGINE + engine->id, + TASK_UNINTERRUPTIBLE); + } } intel_gt_reset_global(gt, engine_mask, msg); - for_each_engine(engine, gt, tmp) - clear_bit_unlock(I915_RESET_ENGINE + engine->id, - &gt->reset.flags); + if (!intel_uc_uses_guc_submission(&gt->uc)) { + for_each_engine(engine, gt, tmp) + clear_bit_unlock(I915_RESET_ENGINE + engine->id, + &gt->reset.flags); + } clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags); smp_mb__after_atomic(); wake_up_all(&gt->reset.queue); -- 2.32.0

2 1

[v1] drm/msm/disp/dpu1: set default group ID for CTL.
by Kalyan Thota 28 Oct '21

28 Oct '21

From: Kalyan Thota <kalyan_t(a)codeaurora.org> New required programming in CTL for SC7280. Group ID informs HW of which VM owns that CTL. Force this group ID to default/disabled until virtualization support is enabled in SW. Signed-off-by: Kalyan Thota <quic_kalyant(a)quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ce6f32a..283605c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -45,7 +45,7 @@ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE)) + (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG)) #define MERGE_3D_SM8150_MASK (0) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4ade44b..57b9be1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -179,13 +179,16 @@ enum { /** * CTL sub-blocks - * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display + * @DPU_CTL_SPLIT_DISPLAY, CTL supports video mode split display + * @DPU_CTL_FETCH_ACTIVE, Active CTL for fetch HW (SSPPs). + * @DPU_CTL_VM_CFG, CTL supports multiple VMs. * @DPU_CTL_MAX */ enum { DPU_CTL_SPLIT_DISPLAY = 0x1, DPU_CTL_ACTIVE_CFG, DPU_CTL_FETCH_ACTIVE, + DPU_CTL_VM_CFG, DPU_CTL_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 64740ddb..455b06a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -498,6 +498,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 mode_sel = 0; + if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features))) + mode_sel = 0xf0000000; + if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD) mode_sel |= BIT(17); -- 2.7.4

2 1

[PATCH v4 0/5] drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
by Lyude Paul 28 Oct '21

28 Oct '21

When I originally moved all of the VESA backlight code in i915 into DRM helpers, one of the things I didn't have the hardware or time for testing was machines that used a combination of PWM and DPCD in order to control their backlights. This has since then caused some breakages and resulted in us disabling DPCD backlight support on such machines. This works fine, unless you have a machine that actually needs this functionality for backlight controls to work at all. Additionally, we will need to support PWM for when we start adding support for VESA's product (as in the product of multiplication) control mode for better brightness ranges. So - let's finally finish up implementing basic support for these types of backlights to solve these problems in our DP helpers, along with implementing support for this in i915. And since digging into this issue solved the last questions we really had about probing backlights in i915 for the most part, let's update some of the comments around that as well! Changes (v3): * Add likely fix for weird backlight scaling issues on samus-fi-bdw in intel's CI, which pointed out we've been leaving some (currently) unsupported backlight features on by mistake which certainly have the potential to cause problems. UPDATE: this didn't fix the problem, but this changed the symptoms was definitely still a bug either way. Changes (v2): * Fixup docs * Add patch to stop us from breaking nouveau Lyude Paul (5): drm/i915: Add support for panels with VESA backlights with PWM enable/disable drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux enable/brightness drm/dp: Disable unsupported features in DP_EDP_BACKLIGHT_MODE_SET_REGISTER drm/dp, drm/i915: Add support for VESA backlights using PWM for brightness control drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs() drivers/gpu/drm/drm_dp_helper.c | 82 +++++++++++++------ .../drm/i915/display/intel_dp_aux_backlight.c | 81 ++++++++++++++---- drivers/gpu/drm/nouveau/nouveau_backlight.c | 5 +- include/drm/drm_dp_helper.h | 7 +- 4 files changed, 129 insertions(+), 46 deletions(-) -- 2.31.1

4 9

drm/virtio: not pin pages on demand
by Maksym Wezdecki 28 Oct '21

28 Oct '21

From: mwezdeck <maksym.wezdecki(a)collabora.co.uk> The idea behind the commit: 1. when resource is created, let user space decide if resource should be pinned or not 2. transfer_*_host needs pinned memory. If it is not pinned, then pin it. 3. during execbuffer, decide which bo handles should be pinned based on the list provided by user space This change has no impact on user space. If user space driver would like not to pin pages, for example, for textures only, it can notify guest kernel about that. Then it can use staging buffer for texture uploads from guest to host. Staging buffer is always pinned. Signed-off-by: mwezdeck <maksym.wezdecki(a)collabora.co.uk> diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h index d4e610a44e12..f429b0f48243 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.h +++ b/drivers/gpu/drm/virtio/virtgpu_drv.h @@ -434,6 +434,10 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, struct virtio_gpu_object **bo_ptr, struct virtio_gpu_fence *fence); +int virtio_gpu_object_pin(struct virtio_gpu_device *vgdev, + struct virtio_gpu_object_array *objs, + int num_gem_objects); + bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo); int virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev, diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c b/drivers/gpu/drm/virtio/virtgpu_ioctl.c index 5c1ad1596889..c468f71b47d7 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c +++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c @@ -83,8 +83,11 @@ static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, struct virtio_gpu_fence *out_fence; int ret; uint32_t *bo_handles = NULL; + uint32_t *accessed_bo_handles = NULL; void __user *user_bo_handles = NULL; + void __user *user_accessed_bo_handles = NULL; struct virtio_gpu_object_array *buflist = NULL; + struct virtio_gpu_object_array *acc_buflist = NULL; struct sync_file *sync_file; int in_fence_fd = exbuf->fence_fd; int out_fence_fd = -1; @@ -149,6 +152,44 @@ static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, } kvfree(bo_handles); bo_handles = NULL; + + if (exbuf->flags & VIRTGPU_EXECBUF_ACC_BO_PRESENT && + exbuf->num_acc_bo_handles != 0) { + accessed_bo_handles = + kvmalloc_array(exbuf->num_acc_bo_handles, + sizeof(uint32_t), GFP_KERNEL); + if (!accessed_bo_handles) { + ret = -ENOMEM; + goto out_unused_fd; + } + + user_accessed_bo_handles = + u64_to_user_ptr(exbuf->accessed_bo_handles); + if (copy_from_user(accessed_bo_handles, + user_accessed_bo_handles, + exbuf->num_acc_bo_handles * + sizeof(uint32_t))) { + ret = -EFAULT; + goto out_unused_fd; + } + + acc_buflist = virtio_gpu_array_from_handles( + file, accessed_bo_handles, + exbuf->num_acc_bo_handles); + if (!buflist) { + ret = -ENOENT; + goto out_unused_fd; + } + + ret = virtio_gpu_object_pin(vgdev, acc_buflist, + exbuf->num_acc_bo_handles); + if (ret < 0) { + goto out_unused_fd; + } + + kvfree(accessed_bo_handles); + accessed_bo_handles = NULL; + } } buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size); @@ -226,6 +267,9 @@ static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data, case VIRTGPU_PARAM_CROSS_DEVICE: value = vgdev->has_resource_assign_uuid ? 1 : 0; break; + case VIRTGPU_PARAM_PIN_ON_DEMAND: + value = 1; + break; default: return -EINVAL; } @@ -331,6 +375,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, struct virtio_gpu_object *bo; struct virtio_gpu_object_array *objs; struct virtio_gpu_fence *fence; + struct virtio_gpu_object_shmem *shmem; int ret; u32 offset = args->offset; @@ -348,6 +393,11 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, goto err_put_free; } + shmem = to_virtio_gpu_shmem(bo); + if (!shmem->pages) { + virtio_gpu_object_pin(vgdev, objs, 1); + } + if (!bo->host3d_blob && (args->stride || args->layer_stride)) { ret = -EINVAL; goto err_put_free; @@ -385,6 +435,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, struct drm_virtgpu_3d_transfer_to_host *args = data; struct virtio_gpu_object *bo; struct virtio_gpu_object_array *objs; + struct virtio_gpu_object_shmem *shmem; struct virtio_gpu_fence *fence; int ret; u32 offset = args->offset; @@ -399,6 +450,11 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, goto err_put_free; } + shmem = to_virtio_gpu_shmem(bo); + if (!shmem->pages) { + virtio_gpu_object_pin(vgdev, objs, 1); + } + if (!vgdev->has_virgl_3d) { virtio_gpu_cmd_transfer_to_host_2d (vgdev, offset, diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c index f648b0e24447..ff2e891d7973 100644 --- a/drivers/gpu/drm/virtio/virtgpu_object.c +++ b/drivers/gpu/drm/virtio/virtgpu_object.c @@ -80,9 +80,9 @@ void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo) kfree(shmem->pages); shmem->pages = NULL; drm_gem_shmem_unpin(&bo->base.base); + drm_gem_shmem_free_object(&bo->base.base); } - drm_gem_shmem_free_object(&bo->base.base); } else if (virtio_gpu_is_vram(bo)) { struct virtio_gpu_object_vram *vram = to_virtio_gpu_vram(bo); @@ -219,6 +219,7 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, struct virtio_gpu_mem_entry *ents; unsigned int nents; int ret; + uint32_t backup_flags = params->flags; *bo_ptr = NULL; @@ -246,11 +247,16 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, goto err_put_objs; } - ret = virtio_gpu_object_shmem_init(vgdev, bo, &ents, &nents); - if (ret != 0) { - virtio_gpu_array_put_free(objs); - virtio_gpu_free_object(&shmem_obj->base); - return ret; + // turn off these bits, as renderer doesn't support such bits + params->flags &= ~(VIRTGPU_NOT_PIN_FLAG); + + if (!(backup_flags & VIRTGPU_NOT_PIN_FLAG)) { + ret = virtio_gpu_object_shmem_init(vgdev, bo, &ents, &nents); + if (ret != 0) { + virtio_gpu_array_put_free(objs); + virtio_gpu_free_object(&shmem_obj->base); + return ret; + } } if (params->blob) { @@ -262,11 +268,15 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, } else if (params->virgl) { virtio_gpu_cmd_resource_create_3d(vgdev, bo, params, objs, fence); - virtio_gpu_object_attach(vgdev, bo, ents, nents); + if (!(backup_flags & VIRTGPU_NOT_PIN_FLAG)) { + virtio_gpu_object_attach(vgdev, bo, ents, nents); + } } else { virtio_gpu_cmd_create_resource(vgdev, bo, params, objs, fence); - virtio_gpu_object_attach(vgdev, bo, ents, nents); + if (!(backup_flags & VIRTGPU_NOT_PIN_FLAG)) { + virtio_gpu_object_attach(vgdev, bo, ents, nents); + } } *bo_ptr = bo; @@ -280,3 +290,29 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, drm_gem_shmem_free_object(&shmem_obj->base); return ret; } + +int virtio_gpu_object_pin(struct virtio_gpu_device *vgdev, + struct virtio_gpu_object_array *objs, + int num_gem_objects) +{ + int i, ret; + + for (i = 0; i < num_gem_objects; i++) { + struct virtio_gpu_mem_entry *ents; + unsigned int nents; + + struct virtio_gpu_object *bo = + gem_to_virtio_gpu_obj(objs->objs[i]); + if (!bo) { + return -EFAULT; + } + + ret = virtio_gpu_object_shmem_init(vgdev, bo, &ents, &nents); + if (ret != 0) { + return -EFAULT; + } + + virtio_gpu_object_attach(vgdev, bo, ents, nents); + } + return 0; +} diff --git a/include/uapi/drm/virtgpu_drm.h b/include/uapi/drm/virtgpu_drm.h index b9ec26e9c646..6ae9af4aadea 100644 --- a/include/uapi/drm/virtgpu_drm.h +++ b/include/uapi/drm/virtgpu_drm.h @@ -50,10 +50,17 @@ extern "C" { #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 -#define VIRTGPU_EXECBUF_FLAGS (\ - VIRTGPU_EXECBUF_FENCE_FD_IN |\ - VIRTGPU_EXECBUF_FENCE_FD_OUT |\ - 0) +#define VIRTGPU_EXECBUF_ACC_BO_PRESENT 0x04 +#define VIRTGPU_EXECBUF_FLAGS \ + (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | \ + VIRTGPU_EXECBUF_ACC_BO_PRESENT | 0) + +/* it is used in resource_create_ioctl as resource + * flag. + * First 8 bits of uint32_t and 24th bit + * are reserved for user space driver. + */ +#define VIRTGPU_NOT_PIN_FLAG (1 << 9) struct drm_virtgpu_map { __u64 offset; /* use for mmap system call */ @@ -68,6 +75,8 @@ struct drm_virtgpu_execbuffer { __u64 bo_handles; __u32 num_bo_handles; __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ + __u64 accessed_bo_handles; + __u32 num_acc_bo_handles; }; #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ @@ -75,6 +84,7 @@ struct drm_virtgpu_execbuffer { #define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */ #define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */ #define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */ +#define VIRTGPU_PARAM_PIN_ON_DEMAND 6 /* is pinning on demand available? */ struct drm_virtgpu_getparam { __u64 param;

4 9

Re: mmotm 2021-10-27-18-32 uploaded (drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c)
by Randy Dunlap 28 Oct '21

28 Oct '21

On 10/27/21 6:33 PM, akpm(a)linux-foundation.org wrote: > The mm-of-the-moment snapshot 2021-10-27-18-32 has been uploaded to > > https://www.ozlabs.org/~akpm/mmotm/ > > mmotm-readme.txt says > > README for mm-of-the-moment: > > https://www.ozlabs.org/~akpm/mmotm/ > > This is a snapshot of my -mm patch queue. Uploaded at random hopefully > more than once a week. > > You will need quilt to apply these patches to the latest Linus release (5.x > or 5.x-rcY). The series file is in broken-out.tar.gz and is duplicated in > https://ozlabs.org/~akpm/mmotm/series > > The file broken-out.tar.gz contains two datestamp files: .DATE and > .DATE-yyyy-mm-dd-hh-mm-ss. Both contain the string yyyy-mm-dd-hh-mm-ss, > followed by the base kernel version against which this patch series is to > be applied. On x86_64, when # CONFIG_SMP is not set ../drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c: In function ‘i915_gem_object_get_pages_dmabuf’: ../drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c:251:3: error: implicit declaration of function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? [-Werror=implicit-function-declaration] wbinvd_on_all_cpus(); Full randconfig file is attached. -- ~Randy

1 0

[git pull] drm fixes for 5.15 final
by Dave Airlie 28 Oct '21

28 Oct '21

Hi Linus, Quiet but not too quiet, I blame Halloween. The first set of amdgpu fixes missed last week, hence why this has a few more of them, it's mostly display fixes for new GPUs and some debugfs OOB stuff. The i915 patches have one to remove a tracepoint possible issue before it's a real problem, the others around cflush and display are cc'ed to stable as well. Otherwise it's just a few misc fixes. Dave. drm-fixes-2021-10-29: drm fixes for 5.15 final MAINTAINERS: - change the paths ttm: - Fix fence leak in ttm_transfered_destroy. core: - add GPD Win3 rotation quirk i915: - Remove unconditional clflushes - Fix oops on boot due to sync state on disabled DP encoders - Revert backend specific data added to tracepoints - Remove useless and incorrect memory frequency calculation panel: - Add quirk for Aya Neo 2021 seltest: - Reset property count for each drm damage selftest so full run will work correctly. amdgpu: - Fix two potential out of bounds writes in debugfs - Fix revision handling for Yellow Carp - Display fixes for Yellow Carp - Display fixes for DCN 3.1 The following changes since commit 3906fe9bb7f1a2c8667ae54e967dc8690824f4ea: Linux 5.15-rc7 (2021-10-25 11:30:31 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2021-10-29 for you to fetch changes up to b112166a894db446f47a8c31781b037f28ac1721: MAINTAINERS: dri-devel is for all of drivers/gpu (2021-10-29 04:49:11 +1000) ---------------------------------------------------------------- drm fixes for 5.15 final MAINTAINERS: - change the paths ttm: - Fix fence leak in ttm_transfered_destroy. core: - add GPD Win3 rotation quirk i915: - Remove unconditional clflushes - Fix oops on boot due to sync state on disabled DP encoders - Revert backend specific data added to tracepoints - Remove useless and incorrect memory frequence calculation panel: - Add quirk for Aya Neo 2021 seltest: - Reset property count for each drm damage selftest so full run will work correctly. amdgpu: - Fix two potential out of bounds writes in debugfs - Fix revision handling for Yellow Carp - Display fixes for Yellow Carp - Display fixes for DCN 3.1 ---------------------------------------------------------------- Aaron Liu (1): drm/amdgpu: support B0&B1 external revision id for yellow carp Bryant Mairs (1): drm: panel-orientation-quirks: Add quirk for Aya Neo 2021 Christian König (1): drm/ttm: fix memleak in ttm_transfered_destroy Daniel Vetter (2): drm/i915/selftests: Properly reset mock object propers for each test MAINTAINERS: dri-devel is for all of drivers/gpu Dave Airlie (5): Merge tag 'amd-drm-fixes-5.15-2021-10-21' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes Merge tag 'amd-drm-fixes-5.15-2021-10-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes Merge tag 'drm-misc-fixes-2021-10-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes Merge tag 'drm-misc-fixes-2021-10-28' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes Merge tag 'drm-intel-fixes-2021-10-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes Eric Yang (1): drm/amd/display: increase Z9 latency to workaround underflow in Z9 Imre Deak (1): drm/i915/dp: Skip the HW readout of DPCD on disabled encoders Jake Wang (1): drm/amd/display: Moved dccg init to after bios golden init Joonas Lahtinen (1): drm/i915: Revert 'guc_id' from i915_request tracepoint José Roberto de Souza (1): drm/i915: Remove memory frequency calculation Mario (1): drm: panel-orientation-quirks: Add quirk for GPD Win3 Michael Strauss (1): drm/amd/display: Fallback to clocks which meet requested voltage on DCN31 Nicholas Kazlauskas (3): drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1 drm/amd/display: Require immediate flip support for DCN3.1 planes drm/amd/display: Fix deadlock when falling back to v2 from v3 Nikola Cornij (2): drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1 drm/amd/display: Increase watermark latencies for DCN3.1 Patrik Jakobsson (1): drm/amdgpu: Fix even more out of bound writes from debugfs Thelford Williams (1): drm/amdgpu: fix out of bounds write Ville Syrjälä (2): drm/i915: Convert unconditional clflush to drm_clflush_virt_range() drm/i915: Catch yet another unconditioal clflush MAINTAINERS | 3 +-- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 +++++++-------- .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 29 +++++++++++++-------- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 7 +++-- .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 13 +++++++--- .../amd/display/dc/dml/dcn31/display_mode_vba_31.c | 6 ++--- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 +- .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 6 ++--- drivers/gpu/drm/drm_panel_orientation_quirks.c | 12 +++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ drivers/gpu/drm/i915/gt/intel_timeline.c | 4 +-- drivers/gpu/drm/i915/i915_reg.h | 8 ------ drivers/gpu/drm/i915/i915_trace.h | 7 ++--- drivers/gpu/drm/i915/intel_dram.c | 30 ++-------------------- drivers/gpu/drm/selftests/test-drm_damage_helper.c | 1 + drivers/gpu/drm/ttm/ttm_bo_util.c | 1 + 17 files changed, 72 insertions(+), 82 deletions(-)

2 1

[PATCH][next] nouveau/svm: Use kvcalloc() instead of kvzalloc()
by Gustavo A. R. Silva 28 Oct '21

28 Oct '21

Use 2-factor argument form kvcalloc() instead of kvzalloc(). Link: https://github.com/KSPP/linux/issues/162 Signed-off-by: Gustavo A. R. Silva <gustavoars(a)kernel.org> --- drivers/gpu/drm/nouveau/nouveau_svm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_svm.c b/drivers/gpu/drm/nouveau/nouveau_svm.c index b0c3422cb01f..1a896a24288a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_svm.c +++ b/drivers/gpu/drm/nouveau/nouveau_svm.c @@ -992,7 +992,7 @@ nouveau_svm_fault_buffer_ctor(struct nouveau_svm *svm, s32 oclass, int id) if (ret) return ret; - buffer->fault = kvzalloc(sizeof(*buffer->fault) * buffer->entries, GFP_KERNEL); + buffer->fault = kvcalloc(sizeof(*buffer->fault), buffer->entries, GFP_KERNEL); if (!buffer->fault) return -ENOMEM; -- 2.27.0

3 3

[PATCH] drm/bridge: sn65dsi86: ti_sn65dsi86_read_u16() __maybe_unused
by Bjorn Andersson 28 Oct '21

28 Oct '21

When built without CONFIG_PWM there are no references to ti_sn65dsi86_read_u16(), avoid the W=1 build warning by marking the function as __maybe_unused. __maybe_unused is used insted of a #ifdef guard as it looks slighly cleaner and it avoids issues if in the future other permutations of the config options would use the function. Reported-by: kernel test robot <lkp(a)intel.com> Signed-off-by: Bjorn Andersson <bjorn.andersson(a)linaro.org> --- Robert, I believe you pushed out the driver patch introducing this issue yesterday. Can you please add the relevant Fixes? drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 430067a3071c..e1f43b73155b 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -215,8 +215,8 @@ static const struct regmap_config ti_sn65dsi86_regmap_config = { .cache_type = REGCACHE_NONE, }; -static int ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, - unsigned int reg, u16 *val) +static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, + unsigned int reg, u16 *val) { u8 buf[2]; int ret; -- 2.33.1

2 1

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dri-devel October 2021