dri-devel October 2021

dri-devel@lists.freedesktop.org

347 participants
825 discussions

[PATCH] drm/amdgpu/display: fix build when CONFIG_DRM_AMD_DC_DCN is not set
by Alex Deucher 27 Oct '21

27 Oct '21

Need to guard some things with CONFIG_DRM_AMD_DC_DCN. Fixes: 41724ea273cdda ("drm/amd/display: Add DP 2.0 MST DM Support") Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Cc: Lyude Paul <lyude(a)redhat.com> Cc: Dave Airlie <airlied(a)gmail.com> --- Lyude, can you apply this to topic/amdgpu-dp2.0-mst? or Dave, if it's already pulled can you apply this to drm-next? Thanks! drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a02ca525610c..3f36dbb2c663 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10723,9 +10723,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct dm_crtc_state *dm_old_crtc_state; #if defined(CONFIG_DRM_AMD_DC_DCN) struct dsc_mst_fairness_vars vars[MAX_PIPES]; -#endif struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_topology_mgr *mgr; +#endif trace_amdgpu_dm_atomic_check_begin(state); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 719cbec4c45e..c200e07d2fb2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -219,7 +219,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; bool ret; - u8 link_encoding_cap; + u8 link_encoding_cap = DP_8b_10b_ENCODING; aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; /* Accessing the connector state is required for vcpi_slots allocation @@ -239,7 +239,9 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->port; +#if defined(CONFIG_DRM_AMD_DC_DCN) link_encoding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); +#endif if (enable) { -- 2.31.1

2 1

[PATCH v4 1/2] drm/bridge: parade-ps8640: Enable runtime power management
by Philip Chen 27 Oct '21

27 Oct '21

Fit ps8640 driver into runtime power management framework: First, break _poweron() to 3 parts: (1) turn on power and wait for ps8640's internal MCU to finish init (2) check panel HPD (which is proxied by GPIO9) (3) the other configs. As runtime_resume() can be called before panel is powered, we only add (1) to _resume() and leave (2)(3) to _pre_enable(). We also add (2) to _aux_transfer() as we want to ensure panel HPD is asserted before we start AUX CH transactions. Second, the original driver has a mysterious delay of 50 ms between (2) and (3). Since Parade's support can't explain what the delay is for, and we don't see removing the delay break any boards at hand, remove the delay to fit into this driver change. In addition, rename "powered" to "pre_enabled" and don't check for it in the pm_runtime calls. The pm_runtime calls are already refcounted so there's no reason to check there. The other user of "powered", _get_edid(), only cares if pre_enable() has already been called. Lastly, change some existing DRM_...() logging to dev_...() along the way, since DRM_...() seem to be deprecated in [1]. [1] https://patchwork.freedesktop.org/patch/454760/ Signed-off-by: Philip Chen <philipchen(a)chromium.org> Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Reviewed-by: Stephen Boyd <swboyd(a)chromium.org> --- In v3, I also added pm_suspend_ignore_children() in the ps8640_probe() but forgot to mention that in the v3 change log. Changes in v4: - Make ps8640_ensure_hpd() return int (This change was mis-added to another patch [2] in this patch series: [2] https://patchwork.kernel.org/project/dri-devel/patch/20211026121058.v3.2.I0…) Changes in v3: - Fix typo/wording in the commit message. - Add ps8640_aux_transfer_msg() for AUX operation. In ps8640_aux_transfer(), wrap around ps8640_aux_transfer_msg() with PM operations and HPD check. - Document why autosuspend_delay is set to 500ms. drivers/gpu/drm/bridge/parade-ps8640.c | 186 +++++++++++++++---------- 1 file changed, 115 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 3aaa90913bf8..cf1f630a3958 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -9,6 +9,7 @@ #include <linux/i2c.h> #include <linux/module.h> #include <linux/of_graph.h> +#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> @@ -100,7 +101,7 @@ struct ps8640 { struct regulator_bulk_data supplies[2]; struct gpio_desc *gpio_reset; struct gpio_desc *gpio_powerdown; - bool powered; + bool pre_enabled; }; static const struct regmap_config ps8640_regmap_config[] = { @@ -148,8 +149,29 @@ static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) return container_of(aux, struct ps8640, aux); } -static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, - struct drm_dp_aux_msg *msg) +static int ps8640_ensure_hpd(struct ps8640 *ps_bridge) +{ + struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; + struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev; + int status; + int ret; + + /* + * Apparently something about the firmware in the chip signals that + * HPD goes high by reporting GPIO9 as high (even though HPD isn't + * actually connected to GPIO9). + */ + ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, + status & PS_GPIO9, 20 * 1000, 200 * 1000); + + if (ret < 0) + dev_warn(dev, "HPD didn't go high: %d\n", ret); + + return ret; +} + +static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) { struct ps8640 *ps_bridge = aux_to_ps8640(aux); struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; @@ -274,38 +296,49 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, return len; } -static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, - const enum ps8640_vdo_control ctrl) +static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + struct ps8640 *ps_bridge = aux_to_ps8640(aux); + struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; + int ret; + + pm_runtime_get_sync(dev); + ret = ps8640_ensure_hpd(ps_bridge); + if (!ret) + ret = ps8640_aux_transfer_msg(aux, msg); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, + const enum ps8640_vdo_control ctrl) { struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; + struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; int ret; ret = regmap_bulk_write(map, PAGE3_SET_ADD, vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); - if (ret < 0) { - DRM_ERROR("failed to %sable VDO: %d\n", - ctrl == ENABLE ? "en" : "dis", ret); - return ret; - } - - return 0; + if (ret < 0) + dev_err(dev, "failed to %sable VDO: %d\n", + ctrl == ENABLE ? "en" : "dis", ret); } -static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) +static int __maybe_unused ps8640_resume(struct device *dev) { - struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; - int ret, status; - - if (ps_bridge->powered) - return; + struct ps8640 *ps_bridge = dev_get_drvdata(dev); + int ret; ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), ps_bridge->supplies); if (ret < 0) { - DRM_ERROR("cannot enable regulators %d\n", ret); - return; + dev_err(dev, "cannot enable regulators %d\n", ret); + return ret; } gpiod_set_value(ps_bridge->gpio_powerdown, 0); @@ -314,86 +347,78 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) gpiod_set_value(ps_bridge->gpio_reset, 0); /* - * Wait for the ps8640 embedded MCU to be ready - * First wait 200ms and then check the MCU ready flag every 20ms + * Mystery 200 ms delay for the "MCU to be ready". It's unclear if + * this is truly necessary since the MCU will already signal that + * things are "good to go" by signaling HPD on "gpio 9". See + * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in + * case. */ msleep(200); - ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, - status & PS_GPIO9, 20 * 1000, 200 * 1000); - - if (ret < 0) { - DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", ret); - goto err_regulators_disable; - } - - msleep(50); - - /* - * The Manufacturer Command Set (MCS) is a device dependent interface - * intended for factory programming of the display module default - * parameters. Once the display module is configured, the MCS shall be - * disabled by the manufacturer. Once disabled, all MCS commands are - * ignored by the display interface. - */ - - ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); - if (ret < 0) { - DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret); - goto err_regulators_disable; - } - - /* Switch access edp panel's edid through i2c */ - ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); - if (ret < 0) { - DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret); - goto err_regulators_disable; - } - - ps_bridge->powered = true; - - return; - -err_regulators_disable: - regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), - ps_bridge->supplies); + return 0; } -static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge) +static int __maybe_unused ps8640_suspend(struct device *dev) { + struct ps8640 *ps_bridge = dev_get_drvdata(dev); int ret; - if (!ps_bridge->powered) - return; - gpiod_set_value(ps_bridge->gpio_reset, 1); gpiod_set_value(ps_bridge->gpio_powerdown, 1); ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), ps_bridge->supplies); if (ret < 0) - DRM_ERROR("cannot disable regulators %d\n", ret); + dev_err(dev, "cannot disable regulators %d\n", ret); - ps_bridge->powered = false; + return ret; } +static const struct dev_pm_ops ps8640_pm_ops = { + SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + static void ps8640_pre_enable(struct drm_bridge *bridge) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; + struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; int ret; - ps8640_bridge_poweron(ps_bridge); + pm_runtime_get_sync(dev); + ps8640_ensure_hpd(ps_bridge); + + /* + * The Manufacturer Command Set (MCS) is a device dependent interface + * intended for factory programming of the display module default + * parameters. Once the display module is configured, the MCS shall be + * disabled by the manufacturer. Once disabled, all MCS commands are + * ignored by the display interface. + */ + + ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); + if (ret < 0) + dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); - ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE); + /* Switch access edp panel's edid through i2c */ + ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); if (ret < 0) - ps8640_bridge_poweroff(ps_bridge); + dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); + + ps8640_bridge_vdo_control(ps_bridge, ENABLE); + + ps_bridge->pre_enabled = true; } static void ps8640_post_disable(struct drm_bridge *bridge) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + ps_bridge->pre_enabled = false; + ps8640_bridge_vdo_control(ps_bridge, DISABLE); - ps8640_bridge_poweroff(ps_bridge); + pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); } static int ps8640_bridge_attach(struct drm_bridge *bridge, @@ -474,7 +499,7 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, struct drm_connector *connector) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); - bool poweroff = !ps_bridge->powered; + bool poweroff = !ps_bridge->pre_enabled; struct edid *edid; /* @@ -512,6 +537,12 @@ static const struct drm_bridge_funcs ps8640_bridge_funcs = { .pre_enable = ps8640_pre_enable, }; +static void ps8640_runtime_disable(void *data) +{ + pm_runtime_dont_use_autosuspend(data); + pm_runtime_disable(data); +} + static int ps8640_probe(struct i2c_client *client) { struct device *dev = &client->dev; @@ -587,6 +618,18 @@ static int ps8640_probe(struct i2c_client *client) ps_bridge->aux.transfer = ps8640_aux_transfer; drm_dp_aux_init(&ps_bridge->aux); + pm_runtime_enable(dev); + /* + * In practice, ps8640_aux_transfer_msg() takes ~300ms to complete in + * the worst case. Set autosuspend_delay to 500ms. + */ + pm_runtime_set_autosuspend_delay(dev, 500); + pm_runtime_use_autosuspend(dev); + pm_suspend_ignore_children(dev, true); + ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); + if (ret) + return ret; + drm_bridge_add(&ps_bridge->bridge); return 0; @@ -613,6 +656,7 @@ static struct i2c_driver ps8640_driver = { .driver = { .name = "ps8640", .of_match_table = ps8640_match, + .pm = &ps8640_pm_ops, }, }; module_i2c_driver(ps8640_driver); -- 2.33.0.1079.g6e70778dc9-goog

2 6

[PATCH -next] i915/gem/dmabuf: add <asm/smp.h> to fix build error
by Randy Dunlap 27 Oct '21

27 Oct '21

When CONFIG_SMP is not set, wbinvd_on_all_cpus() is not declared, due to missing <asm/smp.h>. Fixes this build error: ../drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c: In function 'i915_gem_object_get_pages_dmabuf': ../drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c:251:3: error: implicit declaration of function 'wbinvd_on_all_cpus'; did you mean 'wrmsr_on_cpus'? [-Werror=implicit-function-declaration] wbinvd_on_all_cpus(); Fixes: a035154da45d ("drm/i915/dmabuf: add paranoid flush-on-acquire") Signed-off-by: Randy Dunlap <rdunlap(a)infradead.org> To: Jani Nikula <jani.nikula(a)linux.intel.com> Cc: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> Cc: Matthew Auld <matthew.auld(a)intel.com> Cc: Joonas Lahtinen <joonas.lahtinen(a)linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi(a)intel.com> Cc: intel-gfx(a)lists.freedesktop.org Cc: dri-devel(a)lists.freedesktop.org --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 1 + 1 file changed, 1 insertion(+) --- linux-next-20211027.orig/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ linux-next-20211027/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -8,6 +8,7 @@ #include <linux/highmem.h> #include <linux/dma-resv.h> #include <linux/module.h> +#include <asm/smp.h> #include "i915_drv.h" #include "i915_gem_object.h"

1 0

[PATCH] drm/i915/selftests: Allow engine reset failure to do a GT reset in hangcheck selftest
by Matthew Brost 27 Oct '21

27 Oct '21

The hangcheck selftest blocks per engine resets by setting magic bits in the reset flags. This is incorrect for GuC submission because if the GuC fails to reset an engine we would like to do a full GT reset. Do no set these magic bits when using GuC submission. Side note this lockless algorithm with magic bits to block resets really should be ripped out. Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 7e2d99dd012d..90a03c60c80c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -734,7 +734,8 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) reset_engine_count = i915_reset_engine_count(global, engine); st_engine_heartbeat_disable(engine); - set_bit(I915_RESET_ENGINE + id, &gt->reset.flags); + if (!using_guc) + set_bit(I915_RESET_ENGINE + id, &gt->reset.flags); count = 0; do { struct i915_request *rq = NULL; @@ -824,7 +825,8 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) if (err) break; } while (time_before(jiffies, end_time)); - clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags); + if (!using_guc) + clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags); st_engine_heartbeat_enable(engine); pr_info("%s: Completed %lu %s resets\n", engine->name, count, active ? "active" : "idle"); @@ -1042,7 +1044,8 @@ static int __igt_reset_engines(struct intel_gt *gt, yield(); /* start all threads before we begin */ st_engine_heartbeat_disable_no_pm(engine); - set_bit(I915_RESET_ENGINE + id, &gt->reset.flags); + if (!using_guc) + set_bit(I915_RESET_ENGINE + id, &gt->reset.flags); do { struct i915_request *rq = NULL; struct intel_selftest_saved_policy saved; @@ -1165,7 +1168,8 @@ static int __igt_reset_engines(struct intel_gt *gt, if (err) break; } while (time_before(jiffies, end_time)); - clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags); + if (!using_guc) + clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags); st_engine_heartbeat_enable_no_pm(engine); pr_info("i915_reset_engine(%s:%s): %lu resets\n", -- 2.32.0

3 15

[Bug 214847] New: [radeon] UBSAN shows several null-ptr-deref in drm/radeon/atom.c, radeon_atombios.c, atombios_encoders.c, atombios_crtc.c
by bugzilla-daemon＠bugzilla.kernel.org 27 Oct '21

27 Oct '21

https://bugzilla.kernel.org/show_bug.cgi?id=214847 Bug ID: 214847 Summary: [radeon] UBSAN shows several null-ptr-deref in drm/radeon/atom.c, radeon_atombios.c, atombios_encoders.c, atombios_crtc.c Product: Drivers Version: 2.5 Kernel Version: 5.15-rc7 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: erhard_f(a)mailbox.org CC: christian.koenig(a)amd.com Regression: No Created attachment 299331 --> https://bugzilla.kernel.org/attachment.cgi?id=299331&action=edit kernel dmesg (kernel 5.15-rc7, AMD Ryzen 9 5950X) [...] [drm] radeon kernel modesetting enabled. checking generic (e0000000 300000) vs hw (e0000000 10000000) fb0: switching to radeon from simple Console: switching to colour dummy device 80x25 radeon 0000:07:00.0: vgaarb: deactivate vga console [drm] initializing kernel modesetting (RV515 0x1002:0x7187 0x174B:0x3000 0x00). ATOM BIOS: X1550 ================================================================================ UBSAN: null-ptr-deref in drivers/gpu/drm/radeon/atom.c:1400:14 member access within null pointer of type 'ATOM_MASTER_LIST_OF_DATA_TABLES' (aka 'struct _ATOM_MASTER_LIST_OF_DATA_TABLES') CPU: 26 PID: 418 Comm: systemd-udevd Not tainted 5.15.0-rc7-Zen3+ #5 Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./B450M Steel Legend, BIOS P4.20 08/03/2021 Call Trace: dump_stack_lvl+0x7f/0xc0 ubsan_type_mismatch_common+0x248/0x290 __ubsan_handle_type_mismatch_v1+0x49/0x50 atom_allocate_fb_scratch+0x2b/0xf0 [radeon] radeon_atombios_init+0x113/0x130 [radeon] rv515_init+0x5b/0x250 [radeon] radeon_device_init+0x99a/0xe00 [radeon] radeon_driver_load_kms+0xb8/0x1a0 [radeon] drm_dev_register+0xec/0x1d0 [drm] radeon_pci_probe+0xaa/0x100 [radeon] pci_device_probe+0xaa/0x140 really_probe+0x111/0x360 __driver_probe_device+0x84/0xf0 __driver_attach+0xbb/0x120 ? driver_attach+0x20/0x20 bus_for_each_dev+0x93/0xd0 bus_add_driver+0xf5/0x200 driver_register+0x66/0xf0 do_one_initcall+0x11a/0x2e0 ? __kernel_text_address+0x56/0xa0 ? 0xffffffffc0760000 ? mmu_interval_notifier_insert+0xa/0xa0 do_init_module+0x55/0x200 load_module+0x1b50/0x1ee0 ? kernel_read_file_from_fd+0x58/0x80 __x64_sys_finit_module+0xa8/0xd0 do_syscall_64+0x79/0xb0 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7f5c569992c9 Code: 0c 00 b8 ca 00 00 00 0f 05 eb a4 66 0f 1f 44 00 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 6f 1b 0c 00 f7 d8 64 89 01 48 RSP: 002b:00007ffe2a4aefe8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 RAX: ffffffffffffffda RBX: 0000558584ea2070 RCX: 00007f5c569992c9 RDX: 0000000000000000 RSI: 00007f5c56adc97f RDI: 0000000000000016 RBP: 0000000000020000 R08: 0000000000000000 R09: fffffffffffffeb8 R10: 0000000000000016 R11: 0000000000000246 R12: 0000000000000000 R13: 00007f5c56adc97f R14: 0000558584e510c0 R15: 0000000000000000 ================================================================================ ================================================================================ UBSAN: null-ptr-deref in drivers/gpu/drm/radeon/radeon_atombios.c:1126:14 member access within null pointer of type 'ATOM_MASTER_LIST_OF_DATA_TABLES' (aka 'struct _ATOM_MASTER_LIST_OF_DATA_TABLES') CPU: 26 PID: 418 Comm: systemd-udevd Not tainted 5.15.0-rc7-Zen3+ #5 Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./B450M Steel Legend, BIOS P4.20 08/03/2021 Call Trace: dump_stack_lvl+0x7f/0xc0 ubsan_type_mismatch_common+0x248/0x290 __ubsan_handle_type_mismatch_v1+0x49/0x50 radeon_atom_get_clock_info+0x2e/0x410 [radeon] ? atom_allocate_fb_scratch+0xa7/0xf0 [radeon] radeon_get_clock_info+0x170/0x470 [radeon] rv515_init+0xa0/0x250 [radeon] radeon_device_init+0x99a/0xe00 [radeon] radeon_driver_load_kms+0xb8/0x1a0 [radeon] drm_dev_register+0xec/0x1d0 [drm] radeon_pci_probe+0xaa/0x100 [radeon] pci_device_probe+0xaa/0x140 really_probe+0x111/0x360 __driver_probe_device+0x84/0xf0 __driver_attach+0xbb/0x120 ? driver_attach+0x20/0x20 bus_for_each_dev+0x93/0xd0 bus_add_driver+0xf5/0x200 driver_register+0x66/0xf0 do_one_initcall+0x11a/0x2e0 ? __kernel_text_address+0x56/0xa0 ? 0xffffffffc0760000 ? mmu_interval_notifier_insert+0xa/0xa0 do_init_module+0x55/0x200 load_module+0x1b50/0x1ee0 ? kernel_read_file_from_fd+0x58/0x80 __x64_sys_finit_module+0xa8/0xd0 do_syscall_64+0x79/0xb0 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7f5c569992c9 Code: 0c 00 b8 ca 00 00 00 0f 05 eb a4 66 0f 1f 44 00 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 6f 1b 0c 00 f7 d8 64 89 01 48 RSP: 002b:00007ffe2a4aefe8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 RAX: ffffffffffffffda RBX: 0000558584ea2070 RCX: 00007f5c569992c9 RDX: 0000000000000000 RSI: 00007f5c56adc97f RDI: 0000000000000016 RBP: 0000000000020000 R08: 0000000000000000 R09: fffffffffffffeb8 R10: 0000000000000016 R11: 0000000000000246 R12: 0000000000000000 R13: 00007f5c56adc97f R14: 0000558584e510c0 R15: 0000000000000000 ================================================================================ [...] -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

1 2

[PATCH 1/3] fbdev: rework FB_DDC dependencies
by Arnd Bergmann 27 Oct '21

27 Oct '21

From: Arnd Bergmann <arnd(a)arndb.de> Selecting FB_DDC currently turns on CONFIG_I2C implicitly, which is often not desired and can lead to circular dependencies. Change this to a 'depends on' and change all drivers that rely on FB_DDC to have an appropriate I2C dependency as well. Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- drivers/video/fbdev/Kconfig | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index 6ed5e608dd04..c187a93c9a16 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -62,9 +62,8 @@ config FIRMWARE_EDID config FB_DDC tristate - depends on FB + depends on FB && I2C select I2C_ALGOBIT - select I2C config FB_BOOT_VESA_SUPPORT bool @@ -356,6 +355,7 @@ config FB_CYBER2000 config FB_CYBER2000_DDC bool "DDC for CyberPro support" depends on FB_CYBER2000 + depends on I2C=y || I2C=FB_CYBER2000 select FB_DDC default y help @@ -894,6 +894,7 @@ config FB_NVIDIA config FB_NVIDIA_I2C bool "Enable DDC Support" depends on FB_NVIDIA + depends on I2C=y || I2C=FB_NVIDIA select FB_DDC help This enables I2C support for nVidia Chipsets. This is used @@ -940,6 +941,7 @@ config FB_RIVA config FB_RIVA_I2C bool "Enable DDC Support" depends on FB_RIVA + depends on I2C=y || I2C=FB_RIVA select FB_DDC help This enables I2C support for nVidia Chipsets. This is used @@ -967,7 +969,7 @@ config FB_RIVA_BACKLIGHT config FB_I740 tristate "Intel740 support" - depends on FB && PCI + depends on FB && PCI && I2C select FB_MODE_HELPERS select FB_CFB_FILLRECT select FB_CFB_COPYAREA @@ -1021,6 +1023,7 @@ config FB_I810_GTF config FB_I810_I2C bool "Enable DDC Support" depends on FB_I810 && FB_I810_GTF + depends on I2C=y || I2C=FB_I810 select FB_DDC help Add DDC/I2C support for i810fb. This will allow the driver to get @@ -1076,6 +1079,7 @@ config FB_INTEL_DEBUG config FB_INTEL_I2C bool "DDC/I2C for Intel framebuffer support" depends on FB_INTEL + depends on I2C=y || I2C=FB_INTEL select FB_DDC default y help @@ -1155,6 +1159,7 @@ config FB_MATROX_G config FB_MATROX_I2C tristate "Matrox I2C support" depends on FB_MATROX + depends on I2C=y || I2C=FB_MATROX select FB_DDC help This drivers creates I2C buses which are needed for accessing the @@ -1220,6 +1225,7 @@ config FB_RADEON config FB_RADEON_I2C bool "DDC/I2C for ATI Radeon support" depends on FB_RADEON + depends on I2C=y || I2C=FB_RADEON select FB_DDC default y help @@ -1329,6 +1335,7 @@ config FB_S3 config FB_S3_DDC bool "DDC for S3 support" depends on FB_S3 + depends on I2C=y || I2C=FB_S3 select FB_DDC default y help @@ -1354,6 +1361,7 @@ config FB_SAVAGE config FB_SAVAGE_I2C bool "Enable DDC2 Support" depends on FB_SAVAGE + depends on I2C=y || I2C=FB_SAVAGE select FB_DDC help This enables I2C support for S3 Savage Chipsets. This is used @@ -1493,6 +1501,7 @@ config FB_3DFX_ACCEL config FB_3DFX_I2C bool "Enable DDC/I2C support" depends on FB_3DFX + depends on I2C=y || I2C=FB_3DFX select FB_DDC default y help @@ -1532,7 +1541,7 @@ config FB_VT8623 config FB_TRIDENT tristate "Trident/CyberXXX/CyberBlade support" - depends on FB && PCI + depends on FB && PCI && I2C select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- 2.29.2

5 7

dt-bindings: treewide: Update @st.com email address to @foss.st.com
by patrice.chotard＠foss.st.com 27 Oct '21

27 Oct '21

From: Patrice Chotard <patrice.chotard(a)foss.st.com> Not all @st.com email address are concerned, only people who have a specific @foss.st.com email will see their entry updated. For some people, who left the company, remove their email. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- Documentation/devicetree/bindings/arm/sti.yaml | 2 +- Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml | 4 ++-- .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 4 ++-- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 +- Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 2 +- Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml | 2 +- Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml | 2 +- Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 2 +- .../devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml | 2 +- .../devicetree/bindings/display/panel/orisetech,otm8009a.yaml | 2 +- .../devicetree/bindings/display/panel/raydium,rm68200.yaml | 2 +- Documentation/devicetree/bindings/display/st,stm32-dsi.yaml | 4 ++-- Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml | 4 ++-- Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 2 +- Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 2 +- Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml | 2 +- .../devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml | 3 +-- Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 2 +- .../devicetree/bindings/iio/adc/sigma-delta-modulator.yaml | 2 +- Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 2 +- .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++-- Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 2 +- .../bindings/interrupt-controller/st,stm32-exti.yaml | 4 ++-- Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml | 4 ++-- Documentation/devicetree/bindings/media/st,stm32-cec.yaml | 3 +-- Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 2 +- .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 2 +- Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 2 +- Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 3 +-- Documentation/devicetree/bindings/mfd/st,stmfx.yaml | 2 +- Documentation/devicetree/bindings/mfd/st,stpmic1.yaml | 2 +- Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml | 2 +- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 2 +- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++-- Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml | 2 +- Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 2 +- .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 2 +- .../devicetree/bindings/regulator/st,stm32-booster.yaml | 2 +- .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 2 +- .../devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml | 2 +- .../devicetree/bindings/remoteproc/st,stm32-rproc.yaml | 4 ++-- Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 2 +- Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml | 2 +- Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 2 +- Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml | 2 +- Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 2 +- Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 2 +- Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml | 2 +- Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++-- Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++-- .../devicetree/bindings/thermal/st,stm32-thermal.yaml | 2 +- Documentation/devicetree/bindings/timer/st,stm32-timer.yaml | 3 ++- Documentation/devicetree/bindings/usb/st,stusb160x.yaml | 2 +- Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml | 4 ++-- 54 files changed, 67 insertions(+), 69 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml index b1f28d16d3fb..a41cd8764885 100644 --- a/Documentation/devicetree/bindings/arm/sti.yaml +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST STi Platforms Device Tree Bindings maintainers: - - Patrice Chotard <patrice.chotard(a)st.com> + - Patrice Chotard <patrice.chotard(a)foss.st.com> properties: $nodename: diff --git a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml index 8e711bd202fd..ecb28e90fd11 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml @@ -7,8 +7,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 ML-AHB interconnect bindings maintainers: - - Fabien Dessenne <fabien.dessenne(a)st.com> - - Arnaud Pouliquen <arnaud.pouliquen(a)st.com> + - Fabien Dessenne <fabien.dessenne(a)foss.st.com> + - Arnaud Pouliquen <arnaud.pouliquen(a)foss.st.com> description: | These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 149afb5df5af..6f846d69c5e1 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -7,8 +7,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 Platforms System Controller bindings maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> - - Christophe Roullier <christophe.roullier(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> + - Christophe Roullier <christophe.roullier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 9a77ab74be99..e33fbb62b430 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Platforms Device Tree Bindings maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> properties: $nodename: diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index 8b1ecb2ecdd5..a0ae4867ed27 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Reset Clock Controller Binding maintainers: - - Gabriel Fernandez <gabriel.fernandez(a)st.com> + - Gabriel Fernandez <gabriel.fernandez(a)foss.st.com> description: | The RCC IP is both a reset and a clock controller. diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml index cee624c14f07..b72e4858f9aa 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CRC bindings maintainers: - - Lionel Debieve <lionel.debieve(a)st.com> + - Lionel Debieve <lionel.debieve(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml index a4574552502a..ed23bf94a8e0 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CRYP bindings maintainers: - - Lionel Debieve <lionel.debieve(a)st.com> + - Lionel Debieve <lionel.debieve(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index 6dd658f0912c..10ba94792d95 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 HASH bindings maintainers: - - Lionel Debieve <lionel.debieve(a)st.com> + - Lionel Debieve <lionel.debieve(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml index 3c3e51af154b..11fd68a70dca 100644 --- a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare MIPI DSI host controller maintainers: - - Philippe CORNU <philippe.cornu(a)st.com> + - Philippe CORNU <philippe.cornu(a)foss.st.com> description: | This document defines device tree properties for the Synopsys DesignWare MIPI diff --git a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml index 4b6dda6dbc0f..17cbd0ad32bf 100644 --- a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml +++ b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode) maintainers: - - Philippe CORNU <philippe.cornu(a)st.com> + - Philippe CORNU <philippe.cornu(a)foss.st.com> description: | The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml index 39477793d289..e8ce2315631a 100644 --- a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml +++ b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel maintainers: - - Philippe CORNU <philippe.cornu(a)st.com> + - Philippe CORNU <philippe.cornu(a)foss.st.com> description: | The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml index ed310bbe3afe..ce1ef93cce93 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DSI host controller maintainers: - - Philippe Cornu <philippe.cornu(a)st.com> - - Yannick Fertre <yannick.fertre(a)st.com> + - Philippe Cornu <philippe.cornu(a)foss.st.com> + - Yannick Fertre <yannick.fertre(a)foss.st.com> description: The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller. diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index 4ae3d75492d3..01e2da23790b 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 lcd-tft display controller maintainers: - - Philippe Cornu <philippe.cornu(a)st.com> - - Yannick Fertre <yannick.fertre(a)st.com> + - Philippe Cornu <philippe.cornu(a)foss.st.com> + - Yannick Fertre <yannick.fertre(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 4bf676fd25dc..55faab6a468e 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -50,7 +50,7 @@ description: | maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> allOf: - $ref: "dma-controller.yaml#" diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml index c8d2b51d8410..f751796531c9 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> allOf: - $ref: "dma-router.yaml#" diff --git a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml index c30be840be1c..87b4afd2cf62 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml @@ -50,7 +50,7 @@ description: | if no HW ack signal is used by the MDMA client maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> allOf: - $ref: "dma-controller.yaml#" diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml index 47cf9c8d97e9..b18c616035a8 100644 --- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Hardware Spinlock bindings maintainers: - - Benjamin Gaignard <benjamin.gaignard(a)st.com> - - Fabien Dessenne <fabien.dessenne(a)st.com> + - Fabien Dessenne <fabien.dessenne(a)foss.st.com> properties: "#hwlock-cells": diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index d747f4990ad8..c07289a643d8 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: I2C controller embedded in STMicroelectronics STM32 I2C platform maintainers: - - Pierre-Yves MORDRET <pierre-yves.mordret(a)st.com> + - Pierre-Yves MORDRET <pierre-yves.mordret(a)foss.st.com> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml index a390343d0c2a..2287697f1f61 100644 --- a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml +++ b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Device-Tree bindings for sigma delta modulator maintainers: - - Arnaud Pouliquen <arnaud.pouliquen(a)st.com> + - Arnaud Pouliquen <arnaud.pouliquen(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index a58334c3bb76..a055c78cc047 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -19,7 +19,7 @@ description: | Each STM32 ADC block can have up to 3 ADC instances. maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 733351dee252..7c260f209687 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DFSDM ADC device driver maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> - - Olivier Moysan <olivier.moysan(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> description: | STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 393f7005941a..6adeda4087fc 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -15,7 +15,7 @@ description: | current. maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml index 6d3e68eb2e8b..d19c881b4abc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32 External Interrupt Controller Device Tree Bindings maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> - - Ludovic Barre <ludovic.barre(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> + - Ludovic Barre <ludovic.barre(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml index b15da9ba90b2..8eb4bf52ea27 100644 --- a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml @@ -13,8 +13,8 @@ description: channels (N) can be read from a dedicated register. maintainers: - - Fabien Dessenne <fabien.dessenne(a)st.com> - - Arnaud Pouliquen <arnaud.pouliquen(a)st.com> + - Fabien Dessenne <fabien.dessenne(a)foss.st.com> + - Arnaud Pouliquen <arnaud.pouliquen(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml index d75019c093a4..77144cc6f7db 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CEC bindings maintainers: - - Benjamin Gaignard <benjamin.gaignard(a)st.com> - - Yannick Fertre <yannick.fertre(a)st.com> + - Yannick Fertre <yannick.fertre(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 41e1d0cd80e5..9c1262a276b5 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) binding maintainers: - - Hugues Fruchet <hugues.fruchet(a)st.com> + - Hugues Fruchet <hugues.fruchet(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index cba74205846a..6b516d3895af 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -19,7 +19,7 @@ description: | Select. The FMC2 performs only one access at a time to an external device. maintainers: - - Christophe Kerello <christophe.kerello(a)st.com> + - Christophe Kerello <christophe.kerello(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index 8bcea8dd7d90..ec7f0190f46e 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -17,7 +17,7 @@ description: | - simple counter from IN1 input signal. maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index dace35362a7a..10b330d42901 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -17,8 +17,7 @@ description: | programmable prescaler. maintainers: - - Benjamin Gaignard <benjamin.gaignard(a)st.com> - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/st,stmfx.yaml b/Documentation/devicetree/bindings/mfd/st,stmfx.yaml index 19e9afb385ac..b2a4e4aa7ff6 100644 --- a/Documentation/devicetree/bindings/mfd/st,stmfx.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stmfx.yaml @@ -12,7 +12,7 @@ description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C through VDD) and resistive touchscreen controller. maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml b/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml index 305123e74a58..426658ad81d4 100644 --- a/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml @@ -9,7 +9,7 @@ title: STMicroelectonics STPMIC1 Power Management IC bindings description: STMicroelectronics STPMIC1 Power Management IC maintainers: - - pascal Paillet <p.paillet(a)st.com> + - pascal Paillet <p.paillet(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml index 29c5ef24ac6a..eab8ea3da1fa 100644 --- a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings maintainers: - - Christophe Kerello <christophe.kerello(a)st.com> + - Christophe Kerello <christophe.kerello(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 42689b7d03a2..a5c55127cc44 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare MAC Device Tree Bindings maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> - Giuseppe Cavallaro <peppe.cavallaro(a)st.com> - Jose Abreu <joabreu(a)synopsys.com> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index d3f05d5934d5..577f4e284425 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -8,8 +8,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 / MCU DWMAC glue layer controller maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> - - Christophe Roullier <christophe.roullier(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> + - Christophe Roullier <christophe.roullier(a)foss.st.com> description: This file documents platform glue layer for stmmac. diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml index 0b80ce22a2f8..a48c8fa56bce 100644 --- a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml +++ b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml @@ -13,7 +13,7 @@ description: | internal vref (VREFIN_CAL), unique device ID... maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> allOf: - $ref: "nvmem.yaml#" diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 3329f1d33a4f..7bae8dff3ef6 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -24,7 +24,7 @@ description: |_ UTMI switch_______| OTG controller maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index dfee6d38a701..ac88e01ec430 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32 GPIO and Pin Mux/Config controller maintainers: - - Alexandre TORGUE <alexandre.torgue(a)st.com> + - Alexandre TORGUE <alexandre.torgue(a)foss.st.com> description: | STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml index 9f1c70381b82..df0191b1ceba 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 booster for ADC analog input switches bindings maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> description: | Some STM32 devices embed a 3.3V booster supplied by Vdda, that can be used diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml index 3cd4a254e4cb..836d4156d54c 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml @@ -12,7 +12,7 @@ description: | components through the dedicated VREF+ pin. maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> allOf: - $ref: "regulator.yaml#" diff --git a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml index e6322bc3e447..bd07b9c81570 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32MP1 PWR voltage regulators maintainers: - - Pascal Paillet <p.paillet(a)st.com> + - Pascal Paillet <p.paillet(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index 1e6225677e00..b587c97c282b 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -11,8 +11,8 @@ description: boots firmwares on the ST32MP family chipset. maintainers: - - Fabien Dessenne <fabien.dessenne(a)st.com> - - Arnaud Pouliquen <arnaud.pouliquen(a)st.com> + - Fabien Dessenne <fabien.dessenne(a)foss.st.com> + - Arnaud Pouliquen <arnaud.pouliquen(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml index 82bb2e97e889..9a6e4eaf4d3c 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml @@ -11,7 +11,7 @@ description: | IP and is fully separated from other crypto functions. maintainers: - - Lionel Debieve <lionel.debieve(a)st.com> + - Lionel Debieve <lionel.debieve(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml index 5456604b1c14..2359f541b770 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Real Time Clock Bindings maintainers: - - Gabriel Fernandez <gabriel.fernandez(a)st.com> + - Gabriel Fernandez <gabriel.fernandez(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index f50f4ca893a0..333dc42722d2 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# maintainers: - - Erwan Le Ray <erwan.leray(a)st.com> + - Erwan Le Ray <erwan.leray(a)foss.st.com> title: STMicroelectronics STM32 USART bindings diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml index 0d87e2c86a42..963a871e74da 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: CS42L51 audio codec DT bindings maintainers: - - Olivier Moysan <olivier.moysan(a)st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml index 6feb5a09c184..d3966ae04ad0 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 SPI/I2S Controller maintainers: - - Olivier Moysan <olivier.moysan(a)st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> description: The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode. diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index f97132400bb6..1538d11ce9a8 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Serial Audio Interface (SAI) maintainers: - - Olivier Moysan <olivier.moysan(a)st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> description: The SAI interface (Serial Audio Interface) offers a wide set of audio diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml index b7f7dc452231..837e830c47ac 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 S/PDIF receiver (SPDIFRX) maintainers: - - Olivier Moysan <olivier.moysan(a)st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> description: | The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 983c4e54c0be..6ec6f556182f 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings maintainers: - - Christophe Kerello <christophe.kerello(a)st.com> - - Patrice Chotard <patrice.chotard(a)st.com> + - Christophe Kerello <christophe.kerello(a)foss.st.com> + - Patrice Chotard <patrice.chotard(a)foss.st.com> allOf: - $ref: "spi-controller.yaml#" diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 2d9af4c506bb..3d64bed266ac 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -13,8 +13,8 @@ description: | from 4 to 32-bit data size. maintainers: - - Erwan Leray <erwan.leray(a)st.com> - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Erwan Leray <erwan.leray(a)foss.st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> allOf: - $ref: "spi-controller.yaml#" diff --git a/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml b/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml index c0f59c56003d..bee41cff5142 100644 --- a/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 digital thermal sensor (DTS) binding maintainers: - - David Hernandez Sanchez <david.hernandezsanchez(a)st.com> + - Pascal Paillet <p.paillet(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml b/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml index 176aa3c9baf8..937aa8a56366 100644 --- a/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml +++ b/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings maintainers: - - Benjamin Gaignard <benjamin.gaignard(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> + - Patrice Chotard <patrice.chotard(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/usb/st,stusb160x.yaml b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml index 9a51efa9d101..ead1571e0e43 100644 --- a/Documentation/devicetree/bindings/usb/st,stusb160x.yaml +++ b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml @@ -7,7 +7,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STUSB160x Type-C controller bindings maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml index 481bf91f988a..39736449ba64 100644 --- a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml +++ b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Independent WatchDoG (IWDG) bindings maintainers: - - Yannick Fertre <yannick.fertre(a)st.com> - - Christophe Roullier <christophe.roullier(a)st.com> + - Yannick Fertre <yannick.fertre(a)foss.st.com> + - Christophe Roullier <christophe.roullier(a)foss.st.com> allOf: - $ref: "watchdog.yaml#" -- 2.17.1

5 7

[PULL] topic/amdgpu-dp2.0-mst
by Lyude Paul 27 Oct '21

27 Oct '21

topic/amdgpu-dp2.0-mst-2021-10-25: UAPI Changes: Nope! Cross-subsystem Changes: drm_dp_update_payload_part1() takes a new argument for specifying what the VCPI slot start is Core Changes: Make the DP MST helpers aware of the current starting VCPI slot/VCPI total slot count... Driver Changes: ...and then add support for taking advantage of this for 128b/132b links on DP 2.0 for amdgpu The following changes since commit 6f2f7c83303d2227f47551423e507d77d9ea01c7: Merge tag 'drm-intel-gt-next-2021-10-21' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-10-22 06:30:34 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/topic/amdgpu-dp2.0-mst-2021- 10-25 for you to fetch changes up to 41724ea273cdda5261db4fabd6bfb1375fbc96b2: drm/amd/display: Add DP 2.0 MST DM Support (2021-10-25 21:21:09 -0400) ---------------------------------------------------------------- UAPI Changes: Nope! Cross-subsystem Changes: drm_dp_update_payload_part1() takes a new argument for specifying what the VCPI slot start is Core Changes: Make the DP MST helpers aware of the current starting VCPI slot/VCPI total slot count... Driver Changes: ...and then add support for taking advantage of this for 128b/132b links on DP 2.0 for amdgpu ---------------------------------------------------------------- Bhawanpreet Lakha (3): drm: Remove slot checks in dp mst topology during commit drm: Update MST First Link Slot Information Based on Encoding Format drm/amd/display: Add DP 2.0 MST DM Support Fangzhi Zuo (1): drm/amd/display: Add DP 2.0 MST DC Support drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 ++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 292 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 19 ++ drivers/gpu/drm/amd/display/dc/dc_link.h | 7 + drivers/gpu/drm/amd/display/dc/dc_stream.h | 13 + drivers/gpu/drm/drm_dp_mst_topology.c | 42 ++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +- drivers/gpu/drm/radeon/radeon_dp_mst.c | 4 +- include/drm/drm_dp_mst_helper.h | 5 +- 13 files changed, 423 insertions(+), 16 deletions(-)

2 2

[PATCH] drm/mediatek: Do not overwrite user state rotation value.
by Mark Yacoub 27 Oct '21

27 Oct '21

From: Mark Yacoub <markyacoub(a)google.com> [Why] The rotation property must have a valid bitmask value. 0 isn't a valid value. The state should not be overwritten when performing an overlay value check. [How] Do not overwrite state during the check. Resolves: IGT@kms_properties@get_properties-sanity-{atomic,non-atomic} Signed-off-by: Mark Yacoub <markyacoub(a)chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++------------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 5 ++--- 3 files changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 86c3068894b11..2fc566964f68e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -64,7 +64,7 @@ void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); int mtk_ovl_layer_check(struct device *dev, unsigned int idx, - struct mtk_plane_state *mtk_state); + const struct mtk_plane_state *mtk_state); void mtk_ovl_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index ea5760f856ec6..13999564304bc 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -190,19 +190,15 @@ unsigned int mtk_ovl_supported_rotations(struct device *dev) } int mtk_ovl_layer_check(struct device *dev, unsigned int idx, - struct mtk_plane_state *mtk_state) + const struct mtk_plane_state *mtk_state) { - struct drm_plane_state *state = &mtk_state->base; - unsigned int rotation = 0; + const struct drm_plane_state *state = &mtk_state->base; + unsigned int rotation = drm_rotation_simplify( + state->rotation, + DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y); - rotation = drm_rotation_simplify(state->rotation, - DRM_MODE_ROTATE_0 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); - rotation &= ~DRM_MODE_ROTATE_0; - - /* We can only do reflection, not rotation */ - if ((rotation & DRM_MODE_ROTATE_MASK) != 0) + /* We can only do reflection, not non-zero rotation */ + if (((rotation & ~DRM_MODE_ROTATE_0) & DRM_MODE_ROTATE_MASK) != 0) return -EINVAL; /* @@ -212,8 +208,6 @@ int mtk_ovl_layer_check(struct device *dev, unsigned int idx, if (state->fb->format->is_yuv && rotation != 0) return -EINVAL; - state->rotation = rotation; - return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 1b582262b682b..530bdd031933f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -53,9 +53,8 @@ struct mtk_ddp_comp_funcs { void (*disable_vblank)(struct device *dev); unsigned int (*supported_rotations)(struct device *dev); unsigned int (*layer_nr)(struct device *dev); - int (*layer_check)(struct device *dev, - unsigned int idx, - struct mtk_plane_state *state); + int (*layer_check)(struct device *dev, unsigned int idx, + const struct mtk_plane_state *state); void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); -- 2.33.0.1079.g6e70778dc9-goog

1 0

[PATCH v2 1/4] drm/i915/clflush: fixup handling of cache_dirty
by Matthew Auld 27 Oct '21

27 Oct '21

In theory if clflush_work_create() somehow fails here, and we don't yet have mm.pages populated then we end up resetting cache_dirty, which is likely wrong, since that will potentially skip the flush-on-acquire, if it was needed. It looks like intel_user_framebuffer_dirty() can arrive here before the pages are populated. v2(Thomas): - Move setting cache_dirty out of the async portion, also add a comment for why that should still be safe. Signed-off-by: Matthew Auld <matthew.auld(a)intel.com> Cc: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c index f0435c6feb68..47586a8a1b73 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c @@ -109,12 +109,20 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, I915_FENCE_GFP); dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma); dma_fence_work_commit(&clflush->base); + /* + * We must have successfully populated the pages(since we are + * holding a pin on the pages as per the flush worker) to reach + * this point, which must mean we have already done the required + * flush-on-acquire, hence resetting cache_dirty here should be + * safe. + */ + obj->cache_dirty = false; } else if (obj->mm.pages) { __do_clflush(obj); + obj->cache_dirty = false; } else { GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU); } - obj->cache_dirty = false; return true; } -- 2.26.3

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dri-devel October 2021