dri-devel October 2021

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[pull] drm/msm: drm-msm-next-2021-10-26
by Rob Clark 26 Oct '21

26 Oct '21

Hi Dave & Daniel, This is the main pull for v5.16: * eDP support in DP sub-driver (for newer SoCs with native eDP output) * dpu irq handling cleanup * CRC support for making igt happy * Support for NO_CONNECTOR bridges * dsi: 14nm phy support for msm8953 * mdp5: support for msm8x53, sdm450, sdm632 * various smaller fixes and cleanups The following changes since commit c8f01ffc83923a91e8087aaa077de13354a7aa59: drm/msm/dsi: fix off by one in dsi_bus_clk_enable error handling (2021-10-11 17:30:54 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/drm/msm.git drm-msm-next-2021-10-26 for you to fetch changes up to 02d44fde976a8e9330f855fc535180727c779b9b: drm/msm/dp: fix missing #include (2021-10-26 09:31:24 -0700) ---------------------------------------------------------------- Arnd Bergmann (1): drm/msm/dp: fix missing #include Bernard (1): drm/msm: delete conversion from bool value to bool return Bernard Zhao (1): drm/msm: fix warning "using plain integer as NULL pointer" Bjorn Andersson (13): dt-bindings: msm/dp: Change reg definition drm/msm/dp: Use devres for ioremap() drm/msm/dp: Refactor ioremap wrapper drm/msm/dp: Store each subblock in the io region drm/msm/dp: Allow sub-regions to be specified in DT drm/msm/dp: Use the connector passed to dp_debug_get() drm/msm/dp: Simplify the dp_debug debugfs show function drm/msm/dp: Remove global g_dp_display variable drm/msm/dp: Modify prototype of encoder based API drm/msm/dp: Allow specifying connector_type per controller drm/msm/dp: Allow attaching a drm_panel drm/msm/dp: Support up to 3 DP controllers dt-bindings: msm/dp: Add SC8180x compatibles Chi Minghao (1): drm/msm: remove unneeded variable Christophe JAILLET (1): drm: Remove redundant 'flush_workqueue()' calls Colin Ian King (1): drm/msm/dp: Remove redundant initialization of variable bpp Dan Carpenter (5): drm/msm: Fix potential Oops in a6xx_gmu_rpmh_init() drm/msm: potential error pointer dereference in init() drm/msm: unlock on error in get_sched_entity() drm/msm: fix potential NULL dereference in cleanup drm/msm: uninitialized variable in msm_gem_import() David Heidelberg (1): dt-bindings: drm/msm/gpu: convert to YAML Deepak R Varma (1): drm: msm: adreno: use DEFINE_DEBUGFS_ATTRIBUTE with debugfs_create_file_unsafe() Dmitry Baryshkov (7): drm/msm/dpu: squash dpu_core_irq into dpu_hw_interrupts drm/msm/dpu: don't clear IRQ register twice drm/msm/dpu: merge struct dpu_irq into struct dpu_hw_intr drm/msm/dsi: do not enable irq handler before powering up the host drm/msm/dsi: use bulk clk API drm/msm/a6xx: correct cx_debugbus_read arguments drm/msm/hdmi: use bulk regulator API Jessica Zhang (3): drm/msm/dpu: Add CRC support for DPU drm/msm: Fix potential NULL dereference in DPU SSPP drm/msm/dsi: fix wrong type in msm_dsi_host Krishna Manikandan (1): dt-bindings: msm: add DT bindings for sc7280 Marijn Suijten (1): drm/msm/dsi: Use division result from div_u64_rem in 7nm and 14nm PLL Mark Yacoub (1): drm/msm: Change dpu_crtc_get_vblank_counter to use vsync count. Nathan Chancellor (1): drm/msm/dpu: Remove commit and its uses in dpu_crtc_set_crc_source() Rikard Falkeborn (1): drm: msm: hdmi: Constify static structs Rob Clark (6): drm/msm/dsi: Support NO_CONNECTOR bridges drm/msm/dpu: Remove some nonsense drm/msm: Add hrtimer + kthread_work helper drm/msm/devfreq: Add 1ms delay before clamping freq drm/msm/dpu: Remove impossible NULL check drm/msm/dpu: Remove dynamic allocation from atomic context Sireesh Kodali (1): dt-bindings: msm: dsi: Add MSM8953 dsi phy Tim Gardner (1): drm/msm: prevent NULL dereference in msm_gpu_crashstate_capture() Vladimir Lypak (2): drm/msm/dsi: Add phy configuration for MSM8953 drm/msm/mdp5: Add configuration for MDP v1.16 Wang Qing (1): drm: Use IS_ERR() instead of IS_ERR_OR_NULL() Xu Wang (3): drm/msm/mdp4: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare drm/msm: dsi: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare drm/msm/mdp5: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare Yanteng Si (2): drm/msm: Fix missing include files in msm_gem.c drm/msm: Fix missing include files in msm_gem_shrinker.c zhaoxiao (1): drm/msm: Remove initialization of static variables .../bindings/display/msm/dp-controller.yaml | 15 +- .../bindings/display/msm/dpu-sc7280.yaml | 232 ++++++++++++++++ .../bindings/display/msm/dsi-phy-14nm.yaml | 1 + .../devicetree/bindings/display/msm/gpu.txt | 157 ----------- .../devicetree/bindings/display/msm/gpu.yaml | 288 ++++++++++++++++++++ drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 1 - drivers/gpu/drm/msm/Kconfig | 2 + drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 6 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 10 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 256 ------------------ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 147 ++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 19 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 39 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 267 ++++++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 92 +------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 56 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 13 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 70 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 13 - drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 18 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 89 +++++++ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 18 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 12 +- drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c | 8 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 64 ++--- drivers/gpu/drm/msm/dp/dp_debug.c | 294 +++++---------------- drivers/gpu/drm/msm/dp/dp_debug.h | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 143 +++++----- drivers/gpu/drm/msm/dp/dp_display.h | 2 + drivers/gpu/drm/msm/dp/dp_drm.c | 13 +- drivers/gpu/drm/msm/dp/dp_panel.c | 2 +- drivers/gpu/drm/msm/dp/dp_parser.c | 138 ++++++---- drivers/gpu/drm/msm/dp/dp_parser.h | 14 +- drivers/gpu/drm/msm/dsi/dsi.h | 2 + drivers/gpu/drm/msm/dsi/dsi_host.c | 147 +++++------ drivers/gpu/drm/msm/dsi/dsi_manager.c | 66 ++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 25 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 +- drivers/gpu/drm/msm/edp/edp_ctrl.c | 5 +- drivers/gpu/drm/msm/hdmi/hdmi.c | 38 +-- drivers/gpu/drm/msm/hdmi/hdmi.h | 6 +- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 20 +- drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 24 +- drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 33 +-- drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 4 +- drivers/gpu/drm/msm/msm_atomic.c | 21 +- drivers/gpu/drm/msm/msm_drv.c | 33 ++- drivers/gpu/drm/msm/msm_drv.h | 31 ++- drivers/gpu/drm/msm/msm_gem.c | 6 +- drivers/gpu/drm/msm/msm_gem_shrinker.c | 2 + drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 7 + drivers/gpu/drm/msm/msm_gpu_devfreq.c | 38 ++- drivers/gpu/drm/msm/msm_kms.h | 3 +- drivers/gpu/drm/msm/msm_submitqueue.c | 1 + drivers/gpu/drm/tilcdc/tilcdc_drv.c | 4 +- drivers/gpu/drm/vmwgfx/ttm_memory.c | 1 - 68 files changed, 1748 insertions(+), 1321 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/gpu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/gpu.yaml delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c

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[PATCH] backlight: lp855x: Switch to atomic PWM API
by Maíra Canal 26 Oct '21

26 Oct '21

Remove legacy PWM interface (pwm_config, pwm_enable, pwm_disable) and replace it for the atomic PWM API. Signed-off-by: Maíra Canal <maira.canal(a)usp.br> --- drivers/video/backlight/lp855x_bl.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/video/backlight/lp855x_bl.c b/drivers/video/backlight/lp855x_bl.c index e94932c69f54..dd63141a0d26 100644 --- a/drivers/video/backlight/lp855x_bl.c +++ b/drivers/video/backlight/lp855x_bl.c @@ -236,6 +236,7 @@ static void lp855x_pwm_ctrl(struct lp855x *lp, int br, int max_br) unsigned int period = lp->pdata->period_ns; unsigned int duty = br * period / max_br; struct pwm_device *pwm; + struct pwm_state state; /* request pwm device with the consumer name */ if (!lp->pwm) { @@ -244,19 +245,19 @@ static void lp855x_pwm_ctrl(struct lp855x *lp, int br, int max_br) return; lp->pwm = pwm; - - /* - * FIXME: pwm_apply_args() should be removed when switching to - * the atomic PWM API. - */ - pwm_apply_args(pwm); } - pwm_config(lp->pwm, duty, period); + pwm_init_state(pwm, &state); + + state.duty_cycle = duty; + state.period = period; + if (duty) - pwm_enable(lp->pwm); + state.enabled = true; else - pwm_disable(lp->pwm); + state.enabled = false; + + pwm_apply_state(pwm, &state); } static int lp855x_bl_update_status(struct backlight_device *bl) -- 2.31.1

2 1

[PATCH v3 1/2] drm/bridge: parade-ps8640: Enable runtime power management
by Philip Chen 26 Oct '21

26 Oct '21

Fit ps8640 driver into runtime power management framework: First, break _poweron() to 3 parts: (1) turn on power and wait for ps8640's internal MCU to finish init (2) check panel HPD (which is proxied by GPIO9) (3) the other configs. As runtime_resume() can be called before panel is powered, we only add (1) to _resume() and leave (2)(3) to _pre_enable(). We also add (2) to _aux_transfer() as we want to ensure panel HPD is asserted before we start AUX CH transactions. Second, the original driver has a mysterious delay of 50 ms between (2) and (3). Since Parade's support can't explain what the delay is for, and we don't see removing the delay break any boards at hand, remove the delay to fit into this driver change. In addition, rename "powered" to "pre_enabled" and don't check for it in the pm_runtime calls. The pm_runtime calls are already refcounted so there's no reason to check there. The other user of "powered", _get_edid(), only cares if pre_enable() has already been called. Lastly, change some existing DRM_...() logging to dev_...() along the way, since DRM_...() seem to be deprecated in [1]. [1] https://patchwork.freedesktop.org/patch/454760/ Signed-off-by: Philip Chen <philipchen(a)chromium.org> Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- Changes in v3: - Fix typo/wording in the commit message. - Add ps8640_aux_transfer_msg() for AUX operation. In ps8640_aux_transfer(), wrap around ps8640_aux_transfer_msg() with PM operations and HPD check. - Document why autosuspend_delay is set to 500ms. drivers/gpu/drm/bridge/parade-ps8640.c | 186 +++++++++++++++---------- 1 file changed, 115 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 3aaa90913bf8..ac42a3473770 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -9,6 +9,7 @@ #include <linux/i2c.h> #include <linux/module.h> #include <linux/of_graph.h> +#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> @@ -100,7 +101,7 @@ struct ps8640 { struct regulator_bulk_data supplies[2]; struct gpio_desc *gpio_reset; struct gpio_desc *gpio_powerdown; - bool powered; + bool pre_enabled; }; static const struct regmap_config ps8640_regmap_config[] = { @@ -148,8 +149,29 @@ static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) return container_of(aux, struct ps8640, aux); } -static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, - struct drm_dp_aux_msg *msg) +static void ps8640_ensure_hpd(struct ps8640 *ps_bridge) +{ + struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; + struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev; + int status; + int ret; + + /* + * Apparently something about the firmware in the chip signals that + * HPD goes high by reporting GPIO9 as high (even though HPD isn't + * actually connected to GPIO9). + */ + ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, + status & PS_GPIO9, 20 * 1000, 200 * 1000); + + if (ret < 0) + dev_warn(dev, "HPD didn't go high: %d\n", ret); + + return ret; +} + +static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) { struct ps8640 *ps_bridge = aux_to_ps8640(aux); struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; @@ -274,38 +296,49 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, return len; } -static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, - const enum ps8640_vdo_control ctrl) +static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + struct ps8640 *ps_bridge = aux_to_ps8640(aux); + struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; + int ret; + + pm_runtime_get_sync(dev); + ret = ps8640_ensure_hpd(ps_bridge); + if (!ret) + ret = ps8640_aux_transfer_msg(aux, msg); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, + const enum ps8640_vdo_control ctrl) { struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; + struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; int ret; ret = regmap_bulk_write(map, PAGE3_SET_ADD, vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); - if (ret < 0) { - DRM_ERROR("failed to %sable VDO: %d\n", - ctrl == ENABLE ? "en" : "dis", ret); - return ret; - } - - return 0; + if (ret < 0) + dev_err(dev, "failed to %sable VDO: %d\n", + ctrl == ENABLE ? "en" : "dis", ret); } -static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) +static int __maybe_unused ps8640_resume(struct device *dev) { - struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; - int ret, status; - - if (ps_bridge->powered) - return; + struct ps8640 *ps_bridge = dev_get_drvdata(dev); + int ret; ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), ps_bridge->supplies); if (ret < 0) { - DRM_ERROR("cannot enable regulators %d\n", ret); - return; + dev_err(dev, "cannot enable regulators %d\n", ret); + return ret; } gpiod_set_value(ps_bridge->gpio_powerdown, 0); @@ -314,86 +347,78 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) gpiod_set_value(ps_bridge->gpio_reset, 0); /* - * Wait for the ps8640 embedded MCU to be ready - * First wait 200ms and then check the MCU ready flag every 20ms + * Mystery 200 ms delay for the "MCU to be ready". It's unclear if + * this is truly necessary since the MCU will already signal that + * things are "good to go" by signaling HPD on "gpio 9". See + * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in + * case. */ msleep(200); - ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, - status & PS_GPIO9, 20 * 1000, 200 * 1000); - - if (ret < 0) { - DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", ret); - goto err_regulators_disable; - } - - msleep(50); - - /* - * The Manufacturer Command Set (MCS) is a device dependent interface - * intended for factory programming of the display module default - * parameters. Once the display module is configured, the MCS shall be - * disabled by the manufacturer. Once disabled, all MCS commands are - * ignored by the display interface. - */ - - ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); - if (ret < 0) { - DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret); - goto err_regulators_disable; - } - - /* Switch access edp panel's edid through i2c */ - ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); - if (ret < 0) { - DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret); - goto err_regulators_disable; - } - - ps_bridge->powered = true; - - return; - -err_regulators_disable: - regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), - ps_bridge->supplies); + return 0; } -static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge) +static int __maybe_unused ps8640_suspend(struct device *dev) { + struct ps8640 *ps_bridge = dev_get_drvdata(dev); int ret; - if (!ps_bridge->powered) - return; - gpiod_set_value(ps_bridge->gpio_reset, 1); gpiod_set_value(ps_bridge->gpio_powerdown, 1); ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), ps_bridge->supplies); if (ret < 0) - DRM_ERROR("cannot disable regulators %d\n", ret); + dev_err(dev, "cannot disable regulators %d\n", ret); - ps_bridge->powered = false; + return ret; } +static const struct dev_pm_ops ps8640_pm_ops = { + SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + static void ps8640_pre_enable(struct drm_bridge *bridge) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; + struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; int ret; - ps8640_bridge_poweron(ps_bridge); + pm_runtime_get_sync(dev); + ps8640_ensure_hpd(ps_bridge); + + /* + * The Manufacturer Command Set (MCS) is a device dependent interface + * intended for factory programming of the display module default + * parameters. Once the display module is configured, the MCS shall be + * disabled by the manufacturer. Once disabled, all MCS commands are + * ignored by the display interface. + */ + + ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); + if (ret < 0) + dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); - ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE); + /* Switch access edp panel's edid through i2c */ + ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); if (ret < 0) - ps8640_bridge_poweroff(ps_bridge); + dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); + + ps8640_bridge_vdo_control(ps_bridge, ENABLE); + + ps_bridge->pre_enabled = true; } static void ps8640_post_disable(struct drm_bridge *bridge) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + ps_bridge->pre_enabled = false; + ps8640_bridge_vdo_control(ps_bridge, DISABLE); - ps8640_bridge_poweroff(ps_bridge); + pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); } static int ps8640_bridge_attach(struct drm_bridge *bridge, @@ -474,7 +499,7 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, struct drm_connector *connector) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); - bool poweroff = !ps_bridge->powered; + bool poweroff = !ps_bridge->pre_enabled; struct edid *edid; /* @@ -512,6 +537,12 @@ static const struct drm_bridge_funcs ps8640_bridge_funcs = { .pre_enable = ps8640_pre_enable, }; +static void ps8640_runtime_disable(void *data) +{ + pm_runtime_dont_use_autosuspend(data); + pm_runtime_disable(data); +} + static int ps8640_probe(struct i2c_client *client) { struct device *dev = &client->dev; @@ -587,6 +618,18 @@ static int ps8640_probe(struct i2c_client *client) ps_bridge->aux.transfer = ps8640_aux_transfer; drm_dp_aux_init(&ps_bridge->aux); + pm_runtime_enable(dev); + /* + * In practice, ps8640_aux_transfer_msg() takes ~300ms to complete in + * the worst case. Set autosuspend_delay to 500ms. + */ + pm_runtime_set_autosuspend_delay(dev, 500); + pm_runtime_use_autosuspend(dev); + pm_suspend_ignore_children(dev, true); + ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); + if (ret) + return ret; + drm_bridge_add(&ps_bridge->bridge); return 0; @@ -613,6 +656,7 @@ static struct i2c_driver ps8640_driver = { .driver = { .name = "ps8640", .of_match_table = ps8640_match, + .pm = &ps8640_pm_ops, }, }; module_i2c_driver(ps8640_driver); -- 2.33.0.1079.g6e70778dc9-goog

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[PATCH 1/2] drm: Add Gamma and Degamma LUT sizes props to drm_crtc to validate.
by Mark Yacoub 26 Oct '21

26 Oct '21

From: Mark Yacoub <markyacoub(a)google.com> [Why] 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma or Degamma props in the new CRTC state, allowing any invalid size to be passed on. 2. Each driver has its own LUT size, which could also be different for legacy users. [How] 1. Create |degamma_lut_size| and |gamma_lut_size| to save the LUT sizes assigned by the driver when it's initializing its color and CTM management. 2. Create drm_atomic_helper_check_crtc which is called by drm_atomic_helper_check to check the LUT sizes saved in drm_crtc that they match the sizes in the new CRTC state. Fixes: igt@kms_color@pipe-A-invalid-gamma-lut-sizes on MTK Tested on Zork(amdgpu) and Jacuzzi(mediatek) Signed-off-by: Mark Yacoub<markyacoub(a)chromium.org> --- drivers/gpu/drm/drm_atomic_helper.c | 56 +++++++++++++++++++++++++++++ drivers/gpu/drm/drm_color_mgmt.c | 2 ++ include/drm/drm_atomic_helper.h | 1 + include/drm/drm_crtc.h | 11 ++++++ 4 files changed, 70 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 2c0c6ec928200..265b9747250d1 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -930,6 +930,58 @@ drm_atomic_helper_check_planes(struct drm_device *dev, } EXPORT_SYMBOL(drm_atomic_helper_check_planes); +/** + * drm_atomic_helper_check_planes - validate state object for CRTC changes + * @state: the driver state object + * + * Check the CRTC state object such as the Gamma/Degamma LUT sizes if the new + * state holds them. + * + * RETURNS: + * Zero for success or -errno + */ +int drm_atomic_helper_check_crtc(struct drm_atomic_state *state) +{ + struct drm_crtc *crtc; + struct drm_crtc_state *new_crtc_state; + int i; + + for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { + if (new_crtc_state->gamma_lut) { + uint64_t supported_lut_size = crtc->gamma_lut_size; + uint32_t supported_legacy_lut_size = crtc->gamma_size; + uint32_t new_state_lut_size = + drm_color_lut_size(new_crtc_state->gamma_lut); + + if (new_state_lut_size != supported_lut_size && + new_state_lut_size != supported_legacy_lut_size) { + DRM_DEBUG_DRIVER( + "Invalid Gamma LUT size. Should be %u (or %u for legacy) but got %u.\n", + supported_lut_size, + supported_legacy_lut_size, + new_state_lut_size); + return -EINVAL; + } + } + + if (new_crtc_state->degamma_lut) { + uint32_t new_state_lut_size = + drm_color_lut_size(new_crtc_state->degamma_lut); + uint64_t supported_lut_size = crtc->degamma_lut_size; + + if (new_state_lut_size != supported_lut_size) { + DRM_DEBUG_DRIVER( + "Invalid Degamma LUT size. Should be %u but got %u.\n", + supported_lut_size, new_state_lut_size); + return -EINVAL; + } + } + } + + return 0; +} +EXPORT_SYMBOL(drm_atomic_helper_check_crtc); + /** * drm_atomic_helper_check - validate state object * @dev: DRM device @@ -975,6 +1027,10 @@ int drm_atomic_helper_check(struct drm_device *dev, if (ret) return ret; + ret = drm_atomic_helper_check_crtc(state); + if (ret) + return ret; + if (state->legacy_cursor_update) state->async_update = !drm_atomic_helper_async_check(dev, state); diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index bb14f488c8f6c..72a1b628e7cdd 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -166,6 +166,7 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, struct drm_mode_config *config = &dev->mode_config; if (degamma_lut_size) { + crtc->degamma_lut_size = degamma_lut_size; drm_object_attach_property(&crtc->base, config->degamma_lut_property, 0); drm_object_attach_property(&crtc->base, @@ -178,6 +179,7 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, config->ctm_property, 0); if (gamma_lut_size) { + crtc->gamma_lut_size = gamma_lut_size; drm_object_attach_property(&crtc->base, config->gamma_lut_property, 0); drm_object_attach_property(&crtc->base, diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h index 4045e2507e11c..3eda13622ca1e 100644 --- a/include/drm/drm_atomic_helper.h +++ b/include/drm/drm_atomic_helper.h @@ -38,6 +38,7 @@ struct drm_atomic_state; struct drm_private_obj; struct drm_private_state; +int drm_atomic_helper_check_crtc(struct drm_atomic_state *state); int drm_atomic_helper_check_modeset(struct drm_device *dev, struct drm_atomic_state *state); int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state, diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 13eeba2a750af..c602be2cafca9 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1072,6 +1072,17 @@ struct drm_crtc { /** @funcs: CRTC control functions */ const struct drm_crtc_funcs *funcs; + /** + * @degamma_lut_size: Size of degamma LUT. + */ + uint32_t degamma_lut_size; + + /** + * @gamma_lut_size: Size of Gamma LUT. Not used by legacy userspace such as + * X, which doesn't support large lut sizes. + */ + uint32_t gamma_lut_size; + /** * @gamma_size: Size of legacy gamma ramp reported to userspace. Set up * by calling drm_mode_crtc_set_gamma_size(). -- 2.33.0.685.g46640cef36-goog

5 14

[PATCH v2 1/2] drm/bridge: parade-ps8640: Enable runtime power management
by Philip Chen 26 Oct '21

26 Oct '21

Fit ps8640 driver into runtime power management framework: First, break _poweron() to 3 parts: (1) turn on power and wait for ps8640's internal MCU to finish init (2) check panel HPD (which is proxied by GPIO9) (3) the other configs. As runtime_resume() can be called before panel is powered, we only add (1) to _resume() and leave (2)(3) to _pre_enable(). We also add (2) to _aux_transfer() as we want to ensure panel HPD is asserted before we start AUX CH transactions. The original driver has a mysterious delay of 50 ms between (2) and (3). Since Parade's support can't explain what the delay is for, and we don't see removing the delay break any boards at hand, remove the dalay to fit into this driver change. Besides, rename "powered" to "pre_enabled" and don't check for it in the pm_runtime calls. The pm_runtime calls are already refcounted so there's no reason to check there. The other user of "powered", _get_edid(), only cares if pre_enable() has already been called. Lastly, change some existing DRM_...() logging to dev_...() along the way, since DRM_...() seem to be deprecated in [1]. [1] https://patchwork.freedesktop.org/patch/454760/ Signed-off-by: Philip Chen <philipchen(a)chromium.org> Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- (no changes since v1) drivers/gpu/drm/bridge/parade-ps8640.c | 184 +++++++++++++++---------- 1 file changed, 108 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 3aaa90913bf8..220ca3b03d24 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -9,6 +9,7 @@ #include <linux/i2c.h> #include <linux/module.h> #include <linux/of_graph.h> +#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> @@ -100,7 +101,7 @@ struct ps8640 { struct regulator_bulk_data supplies[2]; struct gpio_desc *gpio_reset; struct gpio_desc *gpio_powerdown; - bool powered; + bool pre_enabled; }; static const struct regmap_config ps8640_regmap_config[] = { @@ -148,6 +149,25 @@ static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) return container_of(aux, struct ps8640, aux); } +static void ps8640_ensure_hpd(struct ps8640 *ps_bridge) +{ + struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; + struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev; + int status; + int ret; + + /* + * Apparently something about the firmware in the chip signals that + * HPD goes high by reporting GPIO9 as high (even though HPD isn't + * actually connected to GPIO9). + */ + ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, + status & PS_GPIO9, 20 * 1000, 200 * 1000); + + if (ret < 0) + dev_warn(dev, "HPD didn't go high: %d", ret); +} + static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) { @@ -171,6 +191,9 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, if (msg->address & ~SWAUX_ADDR_MASK) return -EINVAL; + pm_runtime_get_sync(dev); + ps8640_ensure_hpd(ps_bridge); + switch (request) { case DP_AUX_NATIVE_WRITE: case DP_AUX_NATIVE_READ: @@ -180,14 +203,15 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, case DP_AUX_I2C_READ: break; default: - return -EINVAL; + ret = -EINVAL; + goto exit; } ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); if (ret) { DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n", ret); - return ret; + goto exit; } /* Assume it's good */ @@ -213,7 +237,7 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, DRM_DEV_ERROR(dev, "failed to write WDATA: %d\n", ret); - return ret; + goto exit; } } } @@ -228,7 +252,7 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, if (ret) { DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n", ret); - return ret; + goto exit; } switch (data & SWAUX_STATUS_MASK) { @@ -250,9 +274,11 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, len = data & SWAUX_M_MASK; break; case SWAUX_STATUS_INVALID: - return -EOPNOTSUPP; + ret = -EOPNOTSUPP; + goto exit; case SWAUX_STATUS_TIMEOUT: - return -ETIMEDOUT; + ret = -ETIMEDOUT; + goto exit; } if (len && (request == DP_AUX_NATIVE_READ || @@ -264,48 +290,48 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, DRM_DEV_ERROR(dev, "failed to read RDATA: %d\n", ret); - return ret; + goto exit; } buf[i] = data; } } +exit: + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + if (ret) + return ret; return len; } -static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, - const enum ps8640_vdo_control ctrl) +static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, + const enum ps8640_vdo_control ctrl) { struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; + struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; int ret; ret = regmap_bulk_write(map, PAGE3_SET_ADD, vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); - if (ret < 0) { - DRM_ERROR("failed to %sable VDO: %d\n", - ctrl == ENABLE ? "en" : "dis", ret); - return ret; - } - - return 0; + if (ret < 0) + dev_err(dev, "failed to %sable VDO: %d\n", + ctrl == ENABLE ? "en" : "dis", ret); } -static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) +static int __maybe_unused ps8640_resume(struct device *dev) { - struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; - int ret, status; - - if (ps_bridge->powered) - return; + struct ps8640 *ps_bridge = dev_get_drvdata(dev); + int ret; ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), ps_bridge->supplies); if (ret < 0) { - DRM_ERROR("cannot enable regulators %d\n", ret); - return; + dev_err(dev, "cannot enable regulators %d\n", ret); + return ret; } gpiod_set_value(ps_bridge->gpio_powerdown, 0); @@ -314,86 +340,78 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) gpiod_set_value(ps_bridge->gpio_reset, 0); /* - * Wait for the ps8640 embedded MCU to be ready - * First wait 200ms and then check the MCU ready flag every 20ms + * Mystery 200 ms delay for the "MCU to be ready". It's unclear if + * this is truly necessary since the MCU will already signal that + * things are "good to go" by signaling HPD on "gpio 9". See + * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in + * case. */ msleep(200); - ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, - status & PS_GPIO9, 20 * 1000, 200 * 1000); - - if (ret < 0) { - DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", ret); - goto err_regulators_disable; - } - - msleep(50); - - /* - * The Manufacturer Command Set (MCS) is a device dependent interface - * intended for factory programming of the display module default - * parameters. Once the display module is configured, the MCS shall be - * disabled by the manufacturer. Once disabled, all MCS commands are - * ignored by the display interface. - */ - - ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); - if (ret < 0) { - DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret); - goto err_regulators_disable; - } - - /* Switch access edp panel's edid through i2c */ - ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); - if (ret < 0) { - DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret); - goto err_regulators_disable; - } - - ps_bridge->powered = true; - - return; - -err_regulators_disable: - regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), - ps_bridge->supplies); + return 0; } -static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge) +static int __maybe_unused ps8640_suspend(struct device *dev) { + struct ps8640 *ps_bridge = dev_get_drvdata(dev); int ret; - if (!ps_bridge->powered) - return; - gpiod_set_value(ps_bridge->gpio_reset, 1); gpiod_set_value(ps_bridge->gpio_powerdown, 1); ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), ps_bridge->supplies); if (ret < 0) - DRM_ERROR("cannot disable regulators %d\n", ret); + dev_err(dev, "cannot disable regulators %d\n", ret); - ps_bridge->powered = false; + return ret; } +static const struct dev_pm_ops ps8640_pm_ops = { + SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + static void ps8640_pre_enable(struct drm_bridge *bridge) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; + struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; int ret; - ps8640_bridge_poweron(ps_bridge); + pm_runtime_get_sync(dev); + ps8640_ensure_hpd(ps_bridge); - ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE); + /* + * The Manufacturer Command Set (MCS) is a device dependent interface + * intended for factory programming of the display module default + * parameters. Once the display module is configured, the MCS shall be + * disabled by the manufacturer. Once disabled, all MCS commands are + * ignored by the display interface. + */ + + ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); + if (ret < 0) + dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); + + /* Switch access edp panel's edid through i2c */ + ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); if (ret < 0) - ps8640_bridge_poweroff(ps_bridge); + dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); + + ps8640_bridge_vdo_control(ps_bridge, ENABLE); + + ps_bridge->pre_enabled = true; } static void ps8640_post_disable(struct drm_bridge *bridge) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + ps_bridge->pre_enabled = false; + ps8640_bridge_vdo_control(ps_bridge, DISABLE); - ps8640_bridge_poweroff(ps_bridge); + pm_runtime_put_sync(&ps_bridge->page[PAGE0_DP_CNTL]->dev); } static int ps8640_bridge_attach(struct drm_bridge *bridge, @@ -474,7 +492,7 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, struct drm_connector *connector) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); - bool poweroff = !ps_bridge->powered; + bool poweroff = !ps_bridge->pre_enabled; struct edid *edid; /* @@ -512,6 +530,12 @@ static const struct drm_bridge_funcs ps8640_bridge_funcs = { .pre_enable = ps8640_pre_enable, }; +static void ps8640_runtime_disable(void *data) +{ + pm_runtime_dont_use_autosuspend(data); + pm_runtime_disable(data); +} + static int ps8640_probe(struct i2c_client *client) { struct device *dev = &client->dev; @@ -587,6 +611,13 @@ static int ps8640_probe(struct i2c_client *client) ps_bridge->aux.transfer = ps8640_aux_transfer; drm_dp_aux_init(&ps_bridge->aux); + pm_runtime_enable(dev); + pm_runtime_set_autosuspend_delay(dev, 500); + pm_runtime_use_autosuspend(dev); + ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); + if (ret) + return ret; + drm_bridge_add(&ps_bridge->bridge); return 0; @@ -613,6 +644,7 @@ static struct i2c_driver ps8640_driver = { .driver = { .name = "ps8640", .of_match_table = ps8640_match, + .pm = &ps8640_pm_ops, }, }; module_i2c_driver(ps8640_driver); -- 2.33.0.1079.g6e70778dc9-goog

2 5

[PATCH v2] drm: panel-orientation-quirks: Add quirk for GPD Win3
by Mario 26 Oct '21

26 Oct '21

Fixes screen orientation for GPD Win 3 handheld gaming console. Signed-off-by: Mario Risoldi <awxkrnl(a)gmail.com> --- drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c index f6bdec7fa925..f6177c1d9872 100644 --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c @@ -185,6 +185,12 @@ static const struct dmi_system_id orientation_data[] = { DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), }, .driver_data = (void *)&gpd_win2, + }, { /* GPD Win 3 */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "G1618-03") + }, + .driver_data = (void *)&lcd720x1280_rightside_up, }, { /* I.T.Works TW891 */ .matches = { DMI_EXACT_MATCH(DMI_SYS_VENDOR, "To be filled by O.E.M."), -- 2.33.1

2 1

[PATCH v2 0/2] Add support for eDP on SC7280
by Sankeerth Billakanti 26 Oct '21

26 Oct '21

This series will add eDP controller support for Qualcomm SC7280 platform. These patches are baseline changes with which we can enable eDP display on sc7280. The sc7280 eDP controller can also support additional features such as which will be enabled in subsequent patch series. This is based on Bjorn's changes in the below mentioned series to support both eDP and DP programming through the same driver: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=564841 Summary of changes: Changes in V2: - Remove gpio programming from DP driver - Implemented code review comments Changes in V1: - Add support for eDP on SC7280 platform. - Add the new compatible string to documentation. Sankeerth Billakanti (2): drm/msm/dp: Add support for SC7280 eDP dt-bindings: Add SC7280 compatible string .../bindings/display/msm/dp-controller.yaml | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- drivers/gpu/drm/msm/dp/dp_ctrl.c | 20 ++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 4 files changed, 30 insertions(+), 5 deletions(-) -- The Qualcomm Innovatin Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

6 7

[PATCH 0/3] Prepare error capture for asynchronous migration
by Thomas Hellström 26 Oct '21

26 Oct '21

This patch series prepares error capture for asynchronous migration, where the vma pages may not reflect the pages the GPU is currently executing from but may be several migrations ahead. The first patch deals with refcounting sg-list so that they don't disappear under the capture code, which typically otherwise happens at put_pages() time. The second patch introduces vma state snapshots that record the vma state at request submission time. It also updates the memory allocation mode to reflect that error capture may and will happen in the dma-fence signalling critical path, and finally takes additional measures to make sure that the capture list and request is not disappearing from under us while capturing. The latter may otherwise happen if a heartbeat triggered parallel capture is running during a manual reset which retires the request. Finally the last patch is more of a POC patch and not strictly needed yet, but will be (or at least something very similar) soon for async unbinding. It will make sure that unbinding doesn't complete or signal completion before capture is done. Async reuse of memory can't happen until unbinding signals complete and without waiting for capture done, we might capture contents of reused memory. Before the last patch the vma active is instead still keeping the vma alive, but that will not work with async unbinding anymore, and also it is still not clear how we guarantee keeping the vma alive long enough to even grab an active reference during capture. Thomas Hellström (3): drm/i915: Introduce refcounted sg-tables drm/i915: Update error capture code to avoid using the current vma state drm/i915: Initial introduction of vma resources drivers/gpu/drm/i915/Makefile | 1 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 143 ++++++++++--- drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 16 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 188 ++++++++++------- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +- .../drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 180 +++++++++++----- drivers/gpu/drm/i915/i915_request.c | 63 ++++-- drivers/gpu/drm/i915/i915_request.h | 18 +- drivers/gpu/drm/i915/i915_scatterlist.c | 62 ++++-- drivers/gpu/drm/i915/i915_scatterlist.h | 76 ++++++- drivers/gpu/drm/i915/i915_vma.c | 192 +++++++++++++++++- drivers/gpu/drm/i915/i915_vma.h | 15 +- drivers/gpu/drm/i915/i915_vma_snapshot.c | 131 ++++++++++++ drivers/gpu/drm/i915/i915_vma_snapshot.h | 112 ++++++++++ drivers/gpu/drm/i915/i915_vma_types.h | 5 + drivers/gpu/drm/i915/intel_region_ttm.c | 15 +- drivers/gpu/drm/i915/intel_region_ttm.h | 5 +- drivers/gpu/drm/i915/selftests/mock_region.c | 12 +- 21 files changed, 1026 insertions(+), 225 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_vma_snapshot.c create mode 100644 drivers/gpu/drm/i915/i915_vma_snapshot.h -- 2.31.1

2 4

Re: amdgpu "Fatal error during GPU init"; Ryzen 5600G integrated GPU + kernel 5.14.13
by PGNet Dev 26 Oct '21

26 Oct '21

hi >> The driver is not able to find the vbios image which is required for >> the driver to properly enumerate the hardware. I would guess it's a >> platform issue. Is there a newer sbios image available for your >> platform? ... >> I would start with an sbios update is possible. not that i'm aware. this board is an ASRockRack X470D4U server board https://www.asrockrack.com/general/productdetail.asp?Model=X470D4U#Specific… latest BIOS https://www.asrockrack.com/general/productdetail.asp?Model=X470D4U#Download is, 4.20 8/12/2021 BIOS which is installed, dmidecode | grep "BIOS Information" -A5 BIOS Information Vendor: American Megatrends International, LLC. Version: P4.20 Release Date: 04/14/2021 Address: 0xF0000 Runtime Size: 64 kB >> check if there are any options in the >> sbios regarding the behavior of the integrated graphics when an >> external GPU is present. I suspect the one of the following is the >> problem: >> 1. The sbios should disable the integrated graphics when a dGPU is >> present, but due to a bug in the sbios or a particular sbios settings >> it has failed to. >> 2. The sbios should be providing a vbios image for the integrated >> graphics, but due to a bug in the sbios or a particular sbios settings >> it has failed to. >> 3. The platform uses some alternative method to provide access to the >> vbios image for the integrated graphics that Linux does not yet >> handle. Checking on the specific options for Dual/Concurrent GPU support is ... challenging ... so far. I haven't found a clear statement/doc on how it's intended to behave, what options are available, or details on the individual options. Per a chat late last week with ASRockRack, my understanding is that dual CPU support is *supposed* to work. atm, I'm not clear on how specifically test/answer for any of your suspected issues :-/ Reading online to see what to check, etc. > To add to the list - check if ACPI support is broken or skipped. It doesn't appear to me to be; here's dmesg output, dmesg | grep -i acpi ... [ 0.000000] BIOS-e820: [mem 0x000000000a200000-0x000000000a20efff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x00000000bae2e000-0x00000000bae70fff] ACPI data [ 0.000000] BIOS-e820: [mem 0x00000000bae71000-0x00000000bd0defff] ACPI NVS [ 0.000000] reserve setup_data: [mem 0x000000000a200000-0x000000000a20efff] ACPI NVS [ 0.000000] reserve setup_data: [mem 0x00000000bae2e000-0x00000000bae70fff] ACPI data [ 0.000000] reserve setup_data: [mem 0x00000000bae71000-0x00000000bd0defff] ACPI NVS [ 0.000000] efi: ACPI=0xbd0c8000 ACPI 2.0=0xbd0c8014 SMBIOS=0xbdd6d000 SMBIOS 3.0=0xbdd6c000 MEMATTR=0xb5ee6698 ESRT=0xb5804518 MOKvar=0xb568b000 RNG=0xbdd9eb18 [ 0.004625] ACPI: Early table checksum verification disabled [ 0.004627] ACPI: RSDP 0x00000000BD0C8014 000024 (v02 ALASKA) [ 0.004630] ACPI: XSDT 0x00000000BD0C7728 0000E4 (v01 ALASKA A M I 01072009 AMI 01000013) [ 0.004634] ACPI: FACP 0x00000000BAE60000 000114 (v06 ALASKA A M I 01072009 AMI 00010013) [ 0.004637] ACPI: DSDT 0x00000000BAE59000 006308 (v02 ALASKA A M I 01072009 INTL 20120913) [ 0.004639] ACPI: FACS 0x00000000BC0C2000 000040 [ 0.004640] ACPI: IVRS 0x00000000BAE70000 0000D0 (v02 AMD AmdTable 00000001 AMD 00000001) [ 0.004642] ACPI: SPMI 0x00000000BAE6F000 000041 (v05 ALASKA A M I 00000000 AMI. 00000000) [ 0.004644] ACPI: SPMI 0x00000000BAE6E000 000041 (v05 ALASKA A M I 00000000 AMI. 00000000) [ 0.004645] ACPI: SSDT 0x00000000BAE66000 007229 (v02 AMD MYRTLE 00000002 MSFT 04000000) [ 0.004647] ACPI: SSDT 0x00000000BAE62000 003BD7 (v01 AMD AMD AOD 00000001 INTL 20120913) [ 0.004648] ACPI: SSDT 0x00000000BAE61000 0000C8 (v02 ALASKA CPUSSDT 01072009 AMI 01072009) [ 0.004650] ACPI: FIDT 0x00000000BAE58000 00009C (v01 ALASKA A M I 01072009 AMI 00010013) [ 0.004651] ACPI: MCFG 0x00000000BAE57000 00003C (v01 ALASKA A M I 01072009 MSFT 00010013) [ 0.004653] ACPI: AAFT 0x00000000BAE56000 000068 (v01 ALASKA OEMAAFT 01072009 MSFT 00000097) [ 0.004654] ACPI: HPET 0x00000000BAE55000 000038 (v01 ALASKA A M I 01072009 AMI 00000005) [ 0.004656] ACPI: SPCR 0x00000000BAE54000 000050 (v02 A M I APTIO V 01072009 AMI. 00050011) [ 0.004657] ACPI: SSDT 0x00000000BAE51000 002B44 (v02 AMD AmdTable 00000001 AMD 00000001) [ 0.004659] ACPI: CRAT 0x00000000BAE50000 000B68 (v01 AMD AmdTable 00000001 AMD 00000001) [ 0.004660] ACPI: CDIT 0x00000000BAE4F000 000029 (v01 AMD AmdTable 00000001 AMD 00000001) [ 0.004662] ACPI: SSDT 0x00000000BAE4E000 000D53 (v01 AMD MYRTLEG2 00000001 INTL 20120913) [ 0.004663] ACPI: SSDT 0x00000000BAE4D000 00022A (v01 AMD MYRTLEGP 00000001 INTL 20120913) [ 0.004665] ACPI: SSDT 0x00000000BAE49000 00381A (v01 AMD MYRTLE 00000001 INTL 20120913) [ 0.004666] ACPI: SSDT 0x00000000BAE48000 0000BF (v01 AMD AmdTable 00001000 INTL 20120913) [ 0.004668] ACPI: WSMT 0x00000000BAE47000 000028 (v01 ALASKA A M I 01072009 AMI 00010013) [ 0.004669] ACPI: APIC 0x00000000BAE46000 00015E (v03 ALASKA A M I 01072009 AMI 00010013) [ 0.004671] ACPI: SSDT 0x00000000BAE45000 00051B (v01 AMD MYRTLERN 00000001 INTL 20120913) [ 0.004672] ACPI: SSDT 0x00000000BAE43000 0010AF (v01 AMD MYRTLE 00000001 INTL 20120913) [ 0.004674] ACPI: FPDT 0x00000000BAE42000 000044 (v01 ALASKA A M I 01072009 AMI 01000013) [ 0.004675] ACPI: Reserving FACP table memory at [mem 0xbae60000-0xbae60113] [ 0.004676] ACPI: Reserving DSDT table memory at [mem 0xbae59000-0xbae5f307] [ 0.004676] ACPI: Reserving FACS table memory at [mem 0xbc0c2000-0xbc0c203f] [ 0.004677] ACPI: Reserving IVRS table memory at [mem 0xbae70000-0xbae700cf] [ 0.004677] ACPI: Reserving SPMI table memory at [mem 0xbae6f000-0xbae6f040] [ 0.004678] ACPI: Reserving SPMI table memory at [mem 0xbae6e000-0xbae6e040] [ 0.004679] ACPI: Reserving SSDT table memory at [mem 0xbae66000-0xbae6d228] [ 0.004679] ACPI: Reserving SSDT table memory at [mem 0xbae62000-0xbae65bd6] [ 0.004680] ACPI: Reserving SSDT table memory at [mem 0xbae61000-0xbae610c7] [ 0.004680] ACPI: Reserving FIDT table memory at [mem 0xbae58000-0xbae5809b] [ 0.004681] ACPI: Reserving MCFG table memory at [mem 0xbae57000-0xbae5703b] [ 0.004681] ACPI: Reserving AAFT table memory at [mem 0xbae56000-0xbae56067] [ 0.004682] ACPI: Reserving HPET table memory at [mem 0xbae55000-0xbae55037] [ 0.004682] ACPI: Reserving SPCR table memory at [mem 0xbae54000-0xbae5404f] [ 0.004683] ACPI: Reserving SSDT table memory at [mem 0xbae51000-0xbae53b43] [ 0.004683] ACPI: Reserving CRAT table memory at [mem 0xbae50000-0xbae50b67] [ 0.004684] ACPI: Reserving CDIT table memory at [mem 0xbae4f000-0xbae4f028] [ 0.004684] ACPI: Reserving SSDT table memory at [mem 0xbae4e000-0xbae4ed52] [ 0.004685] ACPI: Reserving SSDT table memory at [mem 0xbae4d000-0xbae4d229] [ 0.004686] ACPI: Reserving SSDT table memory at [mem 0xbae49000-0xbae4c819] [ 0.004686] ACPI: Reserving SSDT table memory at [mem 0xbae48000-0xbae480be] [ 0.004687] ACPI: Reserving WSMT table memory at [mem 0xbae47000-0xbae47027] [ 0.004687] ACPI: Reserving APIC table memory at [mem 0xbae46000-0xbae4615d] [ 0.004688] ACPI: Reserving SSDT table memory at [mem 0xbae45000-0xbae4551a] [ 0.004688] ACPI: Reserving SSDT table memory at [mem 0xbae43000-0xbae440ae] [ 0.004689] ACPI: Reserving FPDT table memory at [mem 0xbae42000-0xbae42043] [ 0.070746] ACPI: PM-Timer IO Port: 0x808 [ 0.070752] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) [ 0.070770] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.070771] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) [ 0.070773] ACPI: Using ACPI (MADT) for SMP configuration information [ 0.070774] ACPI: HPET id: 0x10228201 base: 0xfed00000 [ 0.070778] ACPI: SPCR: console: uart,io,0x3f8,115200 [ 0.296452] ACPI: Core revision 20210604 [ 0.418616] ACPI: PM: Registering ACPI NVS region [mem 0x0a200000-0x0a20efff] (61440 bytes) [ 0.418619] ACPI: PM: Registering ACPI NVS region [mem 0xbae71000-0xbd0defff] (36102144 bytes) [ 0.419845] ACPI: bus type PCI registered [ 0.419847] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 [ 0.505757] ACPI: Added _OSI(Module Device) [ 0.505757] ACPI: Added _OSI(Processor Device) [ 0.505757] ACPI: Added _OSI(3.0 _SCP Extensions) [ 0.505757] ACPI: Added _OSI(Processor Aggregator Device) [ 0.505757] ACPI: Added _OSI(Linux-Dell-Video) [ 0.505757] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio) [ 0.505757] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics) [ 0.505757] ACPI: Added _OSI(Linux) [ 0.511109] ACPI BIOS Error (bug): Failure creating named object [\_SB.PCI0.GPP0.VGA], AE_ALREADY_EXISTS (20210604/dswload2-326) [ 0.511115] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20210604/psobject-220) [ 0.511117] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82) [ 0.511119] ACPI BIOS Error (bug): Failure creating named object [\_SB.PCI0.GPP0.HDAU], AE_ALREADY_EXISTS (20210604/dswload2-326) [ 0.511121] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20210604/psobject-220) [ 0.511123] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82) [ 0.511321] ACPI: 11 ACPI AML tables successfully acquired and loaded [ 0.515248] ACPI: Interpreter enabled [ 0.515257] ACPI: PM: (supports S0 S4 S5) [ 0.515258] ACPI: Using IOAPIC for interrupt routing [ 0.515427] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.515619] ACPI: Enabled 4 GPEs in block 00 to 1F [ 0.520321] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.520325] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI EDR HPX-Type3] [ 0.520401] acpi PNP0A08:00: _OSC: platform does not support [SHPCHotplug LTR DPC] [ 0.520471] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] [ 0.520479] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-7f] only partially covers this bridge [ 0.530700] ACPI: PCI: Interrupt link LNKA configured for IRQ 0 [ 0.530727] ACPI: PCI: Interrupt link LNKB configured for IRQ 0 [ 0.530750] ACPI: PCI: Interrupt link LNKC configured for IRQ 0 [ 0.530779] ACPI: PCI: Interrupt link LNKD configured for IRQ 0 [ 0.530805] ACPI: PCI: Interrupt link LNKE configured for IRQ 0 [ 0.530826] ACPI: PCI: Interrupt link LNKF configured for IRQ 0 [ 0.530847] ACPI: PCI: Interrupt link LNKG configured for IRQ 0 [ 0.530868] ACPI: PCI: Interrupt link LNKH configured for IRQ 0 [ 0.531910] ACPI: bus type USB registered [ 0.531910] PCI: Using ACPI for IRQ routing [ 0.543389] pnp: PnP ACPI init [ 0.544422] pnp: PnP ACPI: found 7 devices [ 0.549677] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns [ 0.597052] ACPI: button: Power Button [PWRB] [ 0.597085] ACPI: button: Power Button [PWRF] [ 0.597121] ACPI: \_PR_.C000: Found 3 idle states [ 0.597212] ACPI: \_PR_.C002: Found 3 idle states [ 0.597676] ACPI: \_PR_.C004: Found 3 idle states [ 0.597735] ACPI: \_PR_.C006: Found 3 idle states [ 0.597787] ACPI: \_PR_.C008: Found 3 idle states [ 0.597841] ACPI: \_PR_.C00A: Found 3 idle states [ 0.597891] ACPI: \_PR_.C001: Found 3 idle states [ 0.597936] ACPI: \_PR_.C003: Found 3 idle states [ 0.598059] ACPI: \_PR_.C005: Found 3 idle states [ 0.598201] ACPI: \_PR_.C007: Found 3 idle states [ 0.598327] ACPI: \_PR_.C009: Found 3 idle states [ 0.598411] ACPI: \_PR_.C00B: Found 3 idle states ...

1 2

[PATCH drm-fixes v3] drm/ttm: remove ttm_bo_vm_insert_huge()
by Jason Gunthorpe 26 Oct '21

26 Oct '21

The huge page functionality in TTM does not work safely because PUD and PMD entries do not have a special bit. get_user_pages_fast() considers any page that passed pmd_huge() as usable: if (unlikely(pmd_trans_huge(pmd) || pmd_huge(pmd) || pmd_devmap(pmd))) { And vmf_insert_pfn_pmd_prot() unconditionally sets entry = pmd_mkhuge(pfn_t_pmd(pfn, prot)); eg on x86 the page will be _PAGE_PRESENT | PAGE_PSE. As such gup_huge_pmd() will try to deref a struct page: head = try_grab_compound_head(pmd_page(orig), refs, flags); and thus crash. So, iomem cannot be installed using vmf_insert_pfn_pud/pmd_prot(). Thomas further notices that the drivers are not expecting the struct page to be used by anything - in particular the refcount incr above will cause them to malfunction. This means even the struct page memory cannot be used. Therefore everything about this is not able to fully work correctly considering GUP_fast. Delete it entirely. It can return someday along with a proper PMD/PUD_SPECIAL bit in the page table itself to gate GUP_fast. Cc: stable(a)vger.kernel.org Fixes: 314b6580adc5 ("drm/ttm, drm/vmwgfx: Support huge TTM pagefaults") Reviewed-by: Christian König <christian.koenig(a)amd.com> Reviewed-by: Thomas Hellström <thomas.helllstrom(a)linux.intel.com> Acked-by: Daniel Vetter <daniel.vetter(a)ffwll.ch> Signed-off-by: Jason Gunthorpe <jgg(a)nvidia.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +- drivers/gpu/drm/radeon/radeon_gem.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_vm.c | 94 +--------------------- drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 4 - drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c | 72 +---------------- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c | 3 - include/drm/ttm/ttm_bo_api.h | 3 +- 8 files changed, 7 insertions(+), 175 deletions(-) Daniel/David, please grab it thanks v3: - Updated commit message v2: https://lore.kernel.org/r/0-v2-a44694790652+4ac-ttm_pmd_jgg@nvidia.com - Remove the entire thing as per Thomas's advice v1: https://lore.kernel.org/r/0-v1-69e7da97f81f+21c-ttm_pmd_jgg@nvidia.com Jason diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index d6aa032890ee8b..a1e63ba4c54a59 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -61,7 +61,7 @@ static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) } ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, - TTM_BO_VM_NUM_PREFAULT, 1); + TTM_BO_VM_NUM_PREFAULT); drm_dev_exit(idx); } else { diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 8c2ecc28272322..c89d5964148fd5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -56,7 +56,7 @@ static vm_fault_t nouveau_ttm_fault(struct vm_fault *vmf) nouveau_bo_del_io_reserve_lru(bo); prot = vm_get_page_prot(vma->vm_flags); - ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT, 1); + ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT); nouveau_bo_add_io_reserve_lru(bo); if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index 458f92a7088797..a36a4f2c76b097 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -61,7 +61,7 @@ static vm_fault_t radeon_gem_fault(struct vm_fault *vmf) goto unlock_resv; ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, - TTM_BO_VM_NUM_PREFAULT, 1); + TTM_BO_VM_NUM_PREFAULT); if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) goto unlock_mclk; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index f56be5bc0861ec..e5af7f9e94b273 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -171,89 +171,6 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, } EXPORT_SYMBOL(ttm_bo_vm_reserve); -#ifdef CONFIG_TRANSPARENT_HUGEPAGE -/** - * ttm_bo_vm_insert_huge - Insert a pfn for PUD or PMD faults - * @vmf: Fault data - * @bo: The buffer object - * @page_offset: Page offset from bo start - * @fault_page_size: The size of the fault in pages. - * @pgprot: The page protections. - * Does additional checking whether it's possible to insert a PUD or PMD - * pfn and performs the insertion. - * - * Return: VM_FAULT_NOPAGE on successful insertion, VM_FAULT_FALLBACK if - * a huge fault was not possible, or on insertion error. - */ -static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault *vmf, - struct ttm_buffer_object *bo, - pgoff_t page_offset, - pgoff_t fault_page_size, - pgprot_t pgprot) -{ - pgoff_t i; - vm_fault_t ret; - unsigned long pfn; - pfn_t pfnt; - struct ttm_tt *ttm = bo->ttm; - bool write = vmf->flags & FAULT_FLAG_WRITE; - - /* Fault should not cross bo boundary. */ - page_offset &= ~(fault_page_size - 1); - if (page_offset + fault_page_size > bo->resource->num_pages) - goto out_fallback; - - if (bo->resource->bus.is_iomem) - pfn = ttm_bo_io_mem_pfn(bo, page_offset); - else - pfn = page_to_pfn(ttm->pages[page_offset]); - - /* pfn must be fault_page_size aligned. */ - if ((pfn & (fault_page_size - 1)) != 0) - goto out_fallback; - - /* Check that memory is contiguous. */ - if (!bo->resource->bus.is_iomem) { - for (i = 1; i < fault_page_size; ++i) { - if (page_to_pfn(ttm->pages[page_offset + i]) != pfn + i) - goto out_fallback; - } - } else if (bo->bdev->funcs->io_mem_pfn) { - for (i = 1; i < fault_page_size; ++i) { - if (ttm_bo_io_mem_pfn(bo, page_offset + i) != pfn + i) - goto out_fallback; - } - } - - pfnt = __pfn_to_pfn_t(pfn, PFN_DEV); - if (fault_page_size == (HPAGE_PMD_SIZE >> PAGE_SHIFT)) - ret = vmf_insert_pfn_pmd_prot(vmf, pfnt, pgprot, write); -#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD - else if (fault_page_size == (HPAGE_PUD_SIZE >> PAGE_SHIFT)) - ret = vmf_insert_pfn_pud_prot(vmf, pfnt, pgprot, write); -#endif - else - WARN_ON_ONCE(ret = VM_FAULT_FALLBACK); - - if (ret != VM_FAULT_NOPAGE) - goto out_fallback; - - return VM_FAULT_NOPAGE; -out_fallback: - count_vm_event(THP_FAULT_FALLBACK); - return VM_FAULT_FALLBACK; -} -#else -static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault *vmf, - struct ttm_buffer_object *bo, - pgoff_t page_offset, - pgoff_t fault_page_size, - pgprot_t pgprot) -{ - return VM_FAULT_FALLBACK; -} -#endif - /** * ttm_bo_vm_fault_reserved - TTM fault helper * @vmf: The struct vm_fault given as argument to the fault callback @@ -261,7 +178,6 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault *vmf, * @num_prefault: Maximum number of prefault pages. The caller may want to * specify this based on madvice settings and the size of the GPU object * backed by the memory. - * @fault_page_size: The size of the fault in pages. * * This function inserts one or more page table entries pointing to the * memory backing the buffer object, and then returns a return code @@ -275,8 +191,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault *vmf, */ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, - pgoff_t num_prefault, - pgoff_t fault_page_size) + pgoff_t num_prefault) { struct vm_area_struct *vma = vmf->vma; struct ttm_buffer_object *bo = vma->vm_private_data; @@ -327,11 +242,6 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, prot = pgprot_decrypted(prot); } - /* We don't prefault on huge faults. Yet. */ - if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && fault_page_size != 1) - return ttm_bo_vm_insert_huge(vmf, bo, page_offset, - fault_page_size, prot); - /* * Speculatively prefault a number of pages. Only error on * first page. @@ -429,7 +339,7 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) prot = vma->vm_page_prot; if (drm_dev_enter(ddev, &idx)) { - ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT, 1); + ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT); drm_dev_exit(idx); } else { ret = ttm_bo_vm_dummy_page(vmf, prot); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h index a833751099b559..858aff99a3fe53 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h @@ -1550,10 +1550,6 @@ void vmw_bo_dirty_unmap(struct vmw_buffer_object *vbo, pgoff_t start, pgoff_t end); vm_fault_t vmw_bo_vm_fault(struct vm_fault *vmf); vm_fault_t vmw_bo_vm_mkwrite(struct vm_fault *vmf); -#ifdef CONFIG_TRANSPARENT_HUGEPAGE -vm_fault_t vmw_bo_vm_huge_fault(struct vm_fault *vmf, - enum page_entry_size pe_size); -#endif /* Transparent hugepage support - vmwgfx_thp.c */ #ifdef CONFIG_TRANSPARENT_HUGEPAGE diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c b/drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c index e5a9a5cbd01a7c..922317d1acc8a0 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c @@ -477,7 +477,7 @@ vm_fault_t vmw_bo_vm_fault(struct vm_fault *vmf) else prot = vm_get_page_prot(vma->vm_flags); - ret = ttm_bo_vm_fault_reserved(vmf, prot, num_prefault, 1); + ret = ttm_bo_vm_fault_reserved(vmf, prot, num_prefault); if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; @@ -486,73 +486,3 @@ vm_fault_t vmw_bo_vm_fault(struct vm_fault *vmf) return ret; } - -#ifdef CONFIG_TRANSPARENT_HUGEPAGE -vm_fault_t vmw_bo_vm_huge_fault(struct vm_fault *vmf, - enum page_entry_size pe_size) -{ - struct vm_area_struct *vma = vmf->vma; - struct ttm_buffer_object *bo = (struct ttm_buffer_object *) - vma->vm_private_data; - struct vmw_buffer_object *vbo = - container_of(bo, struct vmw_buffer_object, base); - pgprot_t prot; - vm_fault_t ret; - pgoff_t fault_page_size; - bool write = vmf->flags & FAULT_FLAG_WRITE; - - switch (pe_size) { - case PE_SIZE_PMD: - fault_page_size = HPAGE_PMD_SIZE >> PAGE_SHIFT; - break; -#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD - case PE_SIZE_PUD: - fault_page_size = HPAGE_PUD_SIZE >> PAGE_SHIFT; - break; -#endif - default: - WARN_ON_ONCE(1); - return VM_FAULT_FALLBACK; - } - - /* Always do write dirty-tracking and COW on PTE level. */ - if (write && (READ_ONCE(vbo->dirty) || is_cow_mapping(vma->vm_flags))) - return VM_FAULT_FALLBACK; - - ret = ttm_bo_vm_reserve(bo, vmf); - if (ret) - return ret; - - if (vbo->dirty) { - pgoff_t allowed_prefault; - unsigned long page_offset; - - page_offset = vmf->pgoff - - drm_vma_node_start(&bo->base.vma_node); - if (page_offset >= bo->resource->num_pages || - vmw_resources_clean(vbo, page_offset, - page_offset + PAGE_SIZE, - &allowed_prefault)) { - ret = VM_FAULT_SIGBUS; - goto out_unlock; - } - - /* - * Write protect, so we get a new fault on write, and can - * split. - */ - prot = vm_get_page_prot(vma->vm_flags & ~VM_SHARED); - } else { - prot = vm_get_page_prot(vma->vm_flags); - } - - ret = ttm_bo_vm_fault_reserved(vmf, prot, 1, fault_page_size); - if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) - return ret; - -out_unlock: - dma_resv_unlock(bo->base.resv); - - return ret; -} -#endif diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c index e6b1f98ec99f09..0a4c340252ec4a 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c @@ -61,9 +61,6 @@ int vmw_mmap(struct file *filp, struct vm_area_struct *vma) .fault = vmw_bo_vm_fault, .open = ttm_bo_vm_open, .close = ttm_bo_vm_close, -#ifdef CONFIG_TRANSPARENT_HUGEPAGE - .huge_fault = vmw_bo_vm_huge_fault, -#endif }; struct drm_file *file_priv = filp->private_data; struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index f681bbdbc6982e..36f7eb9d066395 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -594,8 +594,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, - pgoff_t num_prefault, - pgoff_t fault_page_size); + pgoff_t num_prefault); vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf); base-commit: 519d81956ee277b4419c723adfb154603c2565ba -- 2.33.0

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dri-devel October 2021