dri-devel March 2021

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326 participants
867 discussions

[PATCH v13 0/8] drm/mediatek: add support for mediatek SOC MT8183
by Hsin-Yi Wang 17 Mar '21

17 Mar '21

This series is based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next The series is tested on a mt8183 krane device. Change since v12 - fix mtk_dither_config Change since v10, v11 - fix review comments in v9 Change since v9 - change several function to rebase to mediatek-drm-next Change since v8 - fix some review comment in v8 - separate gamma module for mt8183 has no dither function in gamma - enable dither function for 5 or 6 bpc panel display - separate ddp mutex patch from the whole Soc patch Change since v7 - add dt-binding for mt8183 display - base mmsys patch https://patchwork.kernel.org/project/linux-mediatek/cover/1607506379-10998-… - base dts patch https://patchwork.kernel.org/project/linux-mediatek/cover/20201127104930.19… - add mt8183 function call for setting the routing registers - add RDMA fifo size error handle Change since v6 - move ddp component define into mtk_mmsys.h - add mmsys private data to support different ic path connection - add mt8183-mmsys.c to support 8183 path connection - fix reviewed issue in v6 Change since v5 - fix reviewed issue in v5 base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 Change since v4 - fix reviewed issue in v4 Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch Change since v2 - fix reviewed issue in v2 - add mutex node into dts file Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25 Hsin-Yi Wang (1): drm/mediatek: add mtk_dither_set_common() function Yongqiang Niu (7): arm64: dts: mt8183: rename rdma fifo size arm64: dts: mt8183: refine gamma compatible name drm/mediatek: separate gamma module drm/mediatek: add has_dither private data for gamma drm/mediatek: enable dither function soc: mediatek: add mtk mutex support for MT8183 drm/mediatek: add support for mediatek SOC MT8183 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 14 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 198 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 111 ++++------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 49 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/soc/mediatek/mtk-mutex.c | 50 +++++ 10 files changed, 379 insertions(+), 76 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c -- 2.30.0.365.g02bc693789-goog

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[PATCH v1 00/26] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers
by Dmitry Baryshkov 17 Mar '21

17 Mar '21

Restructure MSM DSI PHY drivers. What started as an attempt to grok the overcomplicated PHY drivers, has lead up to the idea of merging PHY and PLL code, reducing abstractions, code duplication, dropping dead code, etc. The patches were mainly tested on RB5 (sm8250, 7nm) and DB410c (apq8016, 28nm-lp) and lightly tested on RB3 (sdm845, 10nm). Changes since RFC: - Reorder patches to move global clock patches in the beginning and dtsi patches where they are required. - remove msm_dsi_phy_set_src_pll() and guess src_pll_id using PHY usecase. The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15: Linux 5.12-rc2 (2021-03-05 17:33:41 -0800) are available in the Git repository at: ssh://git@git.linaro.org/people/dmitry.baryshkov/kernel.git dsi-phy-1 for you to fetch changes up to 79c4c69b676636dac5eab48f33adefbe11246f26: drm/msm/dsi: stop passing src_pll_id to the phy_enable call (2021-03-17 17:34:33 +0300) ---------------------------------------------------------------- Dmitry Baryshkov (26): clk: mux: provide devm_clk_hw_register_mux() clk: divider: add devm_clk_hw_register_divider drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* code drm/msm/dsi: drop multiple pll enable_seq support drm/msm/dsi: move all PLL callbacks into PHY config struct drm/msm/dsi: move min/max PLL rate to phy config drm/msm/dsi: remove msm_dsi_pll_set_usecase drm/msm/dsi: stop setting clock parents manually arm64: dts: qcom: sm8250: assign DSI clock source parents arm64: dts: qcom: sdm845: assign DSI clock source parents drm/msm/dsi: push provided clocks handling into a generic code drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks drm/msm/dsi: use devm_of_clk_add_hw_provider drm/msm/dsi: replace PHY's init callback with configurable data drm/msm/dsi: make save/restore_state phy-level functions drm/msm/dsi: limit vco_delay to 28nm PHY drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy drm/msm/dsi: drop msm_dsi_pll abstracton drm/msm/dsi: drop PLL accessor functions drm/msm/dsi: move ioremaps to dsi_phy_driver_probe drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances drm/msm/dsi: remove temp data from global pll structure drm/msm/dsi: drop global msm_dsi_phy_type enumaration drm/msm/dsi: inline msm_dsi_phy_set_src_pll drm/msm/dsi: stop passing src_pll_id to the phy_enable call arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 + drivers/clk/clk-mux.c | 35 + drivers/gpu/drm/msm/Kconfig | 8 - drivers/gpu/drm/msm/Makefile | 9 - drivers/gpu/drm/msm/dsi/dsi.h | 58 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 51 -- drivers/gpu/drm/msm/dsi/dsi_manager.c | 29 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 150 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 41 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 745 ++++++++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 939 ++++++++++++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 16 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 677 +++++++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 479 +++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 773 +++++++++++++++- drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 184 ---- drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 130 --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 881 ------------------ drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 1096 ----------------------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 643 ------------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 526 ----------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 912 ------------------- include/linux/clk-provider.h | 30 + 24 files changed, 3713 insertions(+), 4711 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c

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[PATCH 0/8] drm/vc4: hdmi: Support the 4k @ 60Hz modes
by Maxime Ripard 17 Mar '21

17 Mar '21

Hi, Here is a series that enables the higher resolutions on the HDMI0 Controller found in the BCM2711 (RPi4). In order to work it needs a few adjustments to config.txt, most notably to enable the enable_hdmi_4kp60 and force_turbo options. The firmware also has a glitch at the moment and will not properly release the BSC controllers, which will make the EDID retrieval fail. We can work around this using the following config.txt options: disable_fw_kms_setup=1 hdmi_edid_file:0=1 hdmi_edid_filename:0=1366x768.bin hdmi_ignore_edid:0=1 hdmi_edid_file:1=1 hdmi_edid_filename:1=1366x768.bin hdmi_ignore_edid:1=1 A fix will come for the firmware eventually. Let me know what you think, Maxime Maxime Ripard (8): clk: Add range accessors drm/vc4: hvs: Make the HVS bind first drm/vc4: hdmi: Properly compute the BVB clock rate drm/vc4: hdmi: Check and warn if we can't reach 4kp60 frequencies drm/vc4: hdmi: Enable the scrambler drm/vc4: hdmi: Raise the maximum clock rate drm/vc4: plane: Fix typo in scaler width and height drm/vc4: plane: Remove redundant assignment drivers/clk/clk.c | 30 ++++++++++ drivers/gpu/drm/vc4/vc4_drv.c | 11 +++- drivers/gpu/drm/vc4/vc4_hdmi.c | 88 ++++++++++++++++++++++++++--- drivers/gpu/drm/vc4/vc4_hdmi.h | 8 +++ drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 3 + drivers/gpu/drm/vc4/vc4_plane.c | 5 +- include/linux/clk.h | 16 ++++++ 7 files changed, 148 insertions(+), 13 deletions(-) -- 2.29.2

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[PATCH] omapdrm/dss/dsi.c:modify 'u32'->'int'
by ChunyouTang 17 Mar '21

17 Mar '21

From: tangchunyou <tangchunyou(a)yulong.com> 1.the type of mipi_dsi_create_packet id int 2.u32 can not < 0 Signed-off-by: tangchunyou <tangchunyou(a)yulong.com> --- drivers/gpu/drm/omapdrm/dss/dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 8e11612..11c502d 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -2149,7 +2149,7 @@ static int dsi_vc_send_short(struct dsi_data *dsi, int vc, const struct mipi_dsi_msg *msg) { struct mipi_dsi_packet pkt; - u32 r; + int r; r = mipi_dsi_create_packet(&pkt, msg); if (r < 0) -- 1.9.1

2 1

[PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock
by quanyang.wang＠windriver.com 17 Mar '21

17 Mar '21

From: Quanyang Wang <quanyang.wang(a)windriver.com> The Runtime PM subsystem will force the device "fd4a0000.zynqmp-display" to enter suspend state while booting if the following conditions are met: - the usage counter is zero (pm_runtime_get_sync hasn't been called yet) - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node) - no other device in the same power domain (dpdma node has no "power-domains = <&zynqmp_firmware PD_DP>" property) So there is a scenario as below: 1) DP device enters suspend state <- call zynqmp_gpd_power_off 2) zynqmp_disp_crtc_setup_clock <- configurate register VPLL_FRAC_CFG 3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and clear previous VPLL_FRAC_CFG configuration 4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG configuration is corrupted >From above, we can see that pm_runtime_get_sync may clear register VPLL_FRAC_CFG configuration and result the failure of clk enabling. Putting pm_runtime_get_sync at the very beginning of the function zynqmp_disp_crtc_atomic_enable can resolve this issue. Signed-off-by: Quanyang Wang <quanyang.wang(a)windriver.com> --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index 148add0ca1d6..909e6c265406 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -1445,9 +1445,10 @@ zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; int ret, vrefresh; + pm_runtime_get_sync(disp->dev); + zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode); - pm_runtime_get_sync(disp->dev); ret = clk_prepare_enable(disp->pclk); if (ret) { dev_err(disp->dev, "failed to enable a pixel clock\n"); -- 2.25.1

5 6

[Bug 212311] New: amdgpu DCN callis sleeping function in illegal context
by bugzilla-daemon＠bugzilla.kernel.org 17 Mar '21

17 Mar '21

https://bugzilla.kernel.org/show_bug.cgi?id=212311 Bug ID: 212311 Summary: amdgpu DCN callis sleeping function in illegal context Product: Drivers Version: 2.5 Kernel Version: 5.11.0 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: nirmoy.aiemd(a)gmail.com Regression: No Getting below warning on boot with Navi10 [ 25.204238] [drm] reserve 0x900000 from 0x81fe400000 for PSP TMR [ 25.243138] amdgpu 0000:44:00.0: amdgpu: RAS: optional ras ta ucode is not available [ 25.247390] amdgpu 0000:44:00.0: amdgpu: RAP: optional rap ta ucode is not available [ 25.247393] amdgpu 0000:44:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available [ 25.247497] amdgpu 0000:44:00.0: amdgpu: use vbios provided pptable [ 25.247499] amdgpu 0000:44:00.0: amdgpu: smc_dpm_info table revision(format.content): 4.5 [ 25.283692] amdgpu 0000:44:00.0: amdgpu: SMU is initialized successfully! [ 25.283718] BUG: sleeping function called from invalid context at include/linux/sched/mm.h:196 [ 25.283735] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 373, name: kworker/6:2 [ 25.283749] 2 locks held by kworker/6:2/373: [ 25.283751] #0: ffff9e7b07c59148 ((wq_completion)events){....}-{0:0}, at: process_one_work+0x1fb/0x4f0 [ 25.283760] #1: ffffaab6441c3e68 ((work_completion)(&wfc.work)){....}-{0:0}, at: process_one_work+0x1fb/0x4f0 [ 25.283768] CPU: 6 PID: 373 Comm: kworker/6:2 Tainted: G E 5.11.0-1-default+ #171 [ 25.283770] Hardware name: Gigabyte Technology Co., Ltd. X399 DESIGNARE EX/X399 DESIGNARE EX-CF, BIOS F12i 09/24/2019 [ 25.283772] Workqueue: events work_for_cpu_fn [ 25.283776] Call Trace: [ 25.283780] dump_stack+0x6b/0x83 [ 25.283785] ___might_sleep.cold+0xa7/0xb7 [ 25.283789] kmem_cache_alloc_trace+0x30a/0x360 [ 25.283796] dccg2_create+0x2d/0x80 [amdgpu] [ 25.283985] dcn20_resource_construct+0x389/0xd30 [amdgpu] [ 25.284146] ? fs_reclaim_release+0x46/0x80 [ 25.284150] ? dcn20_create_resource_pool+0x25/0x80 [amdgpu] [ 25.284308] ? kmem_cache_alloc_trace+0x1a4/0x360 [ 25.284310] ? __kmalloc+0x1c1/0x3c0 [ 25.284314] dcn20_create_resource_pool+0x3c/0x80 [amdgpu] [ 25.284472] dc_create_resource_pool+0x13f/0x1d0 [amdgpu] [ 25.284627] dc_create+0x203/0x7b0 [amdgpu] [ 25.284783] amdgpu_dm_init.isra.0+0x1de/0x270 [amdgpu] [ 25.284940] ? dev_vprintk_emit+0x12c/0x150 [ 25.284947] ? dev_printk_emit+0x4e/0x65 [ 25.284958] dm_hw_init+0xe/0x20 [amdgpu] [ 25.285111] amdgpu_device_init.cold+0x13e6/0x17ad [amdgpu] [ 25.285265] ? pci_bus_read_config_word+0x49/0x70 [ 25.285271] amdgpu_driver_load_kms+0x64/0x260 [amdgpu] [ 25.285393] amdgpu_pci_probe+0x122/0x1b0 [amdgpu] [ 25.285513] local_pci_probe+0x42/0x80 [ 25.285517] work_for_cpu_fn+0x16/0x20 [ 25.285520] process_one_work+0x28c/0x4f0 [ 25.285526] worker_thread+0x20d/0x3f0 [ 25.285528] ? rescuer_thread+0x390/0x390 [ 25.285531] kthread+0x13a/0x150 [ 25.285534] ? __kthread_bind_mask+0x60/0x60 [ 25.285537] ret_from_fork+0x22/0x30 [ 25.285853] [drm] Display Core initialized with v3.2.127! -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

1 1

[PATCH] backlight: qcom-wled: Use sink_addr for sync toggle
by Marijn Suijten 17 Mar '21

17 Mar '21

From: Obeida Shamoun <oshmoun100(a)googlemail.com> WLED3_SINK_REG_SYNC is, as the name implies, a sink register offset. Therefore, use the sink address as base instead of the ctrl address. This fixes the sync toggle on wled4, which can be observed by the fact that adjusting brightness now works. It has no effect on wled3 because sink and ctrl base addresses are the same. This allows adjusting the brightness without having to disable then reenable the module. Signed-off-by: Obeida Shamoun <oshmoun100(a)googlemail.com> Signed-off-by: Konrad Dybcio <konrad.dybcio(a)somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten(a)somainline.org> --- drivers/video/backlight/qcom-wled.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/backlight/qcom-wled.c b/drivers/video/backlight/qcom-wled.c index 091f07e7c145..fc8b443d10fd 100644 --- a/drivers/video/backlight/qcom-wled.c +++ b/drivers/video/backlight/qcom-wled.c @@ -336,13 +336,13 @@ static int wled3_sync_toggle(struct wled *wled) unsigned int mask = GENMASK(wled->max_string_count - 1, 0); rc = regmap_update_bits(wled->regmap, - wled->ctrl_addr + WLED3_SINK_REG_SYNC, + wled->sink_addr + WLED3_SINK_REG_SYNC, mask, mask); if (rc < 0) return rc; rc = regmap_update_bits(wled->regmap, - wled->ctrl_addr + WLED3_SINK_REG_SYNC, + wled->sink_addr + WLED3_SINK_REG_SYNC, mask, WLED3_SINK_REG_SYNC_CLEAR); return rc; -- 2.30.2

4 3

Re: [PATCH 2/3] media/videobuf1|2: Mark follow_pfn usage as unsafe
by Daniel Vetter 17 Mar '21

17 Mar '21

On Wed, Mar 17, 2021 at 8:22 AM Christoph Hellwig <hch(a)infradead.org> wrote: > On Tue, Mar 16, 2021 at 04:52:44PM +0100, Daniel Vetter wrote: > > My understanding is mostly, but with some objections. And I kinda > > don't want to let this die in a bikeshed and then not getting rid of > > follow_pfn as a result. There's enough people who acked this, and the > > full removal got some nack from Mauro iirc. > > Hmm, ok I must have missed that. I defintively prefer your series over > doing nothing, but killing the dead horse ASAP would be even better. I have a bunch of slow-burner things I need to fix in this area of driver mmaps vs get_user_/follow_ conflicts anyway, I'll add a note to put the horse out of it's misery in due time. We have a few problems still where things might get pinned or used where it really shouldn't be. Can I count that as an ack on the series? You've touched this quite a bit recently. Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

1 0

linux-next: build warning after merge of the drm tree
by Stephen Rothwell 17 Mar '21

17 Mar '21

Hi all, After merging the drm tree, today's linux-next build (htmldocs) produced this warning: include/drm/gpu_scheduler.h:304: warning: Function parameter or member '_score' not described in 'drm_gpu_scheduler' Introduced by commit f2f12eb9c32b ("drm/scheduler: provide scheduler score externally") -- Cheers, Stephen Rothwell

1 0

[PATCH] the print is redundant because platform_get_irq()
by ChunyouTang 17 Mar '21

17 Mar '21

From: tangchunyou <tangchunyou(a)yulong.com> already prints an error. Signed-off-by: tangchunyou <tangchunyou(a)yulong.com> --- drivers/gpu/drm/mediatek/mtk_cec.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c index cb29b64..332a4df 100644 --- a/drivers/gpu/drm/mediatek/mtk_cec.c +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -208,10 +208,8 @@ static int mtk_cec_probe(struct platform_device *pdev) } cec->irq = platform_get_irq(pdev, 0); - if (cec->irq < 0) { - dev_err(dev, "Failed to get cec irq: %d\n", cec->irq); + if (cec->irq < 0) return cec->irq; - } ret = devm_request_threaded_irq(dev, cec->irq, NULL, mtk_cec_htplg_isr_thread, -- 1.9.1

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dri-devel March 2021