dri-devel March 2022

dri-devel@lists.freedesktop.org

370 participants
780 discussions

[PATCH] drm/msm: Add missing put_task_struct() in debugfs path
by Rob Clark 17 Mar '22

17 Mar '22

From: Rob Clark <robdclark(a)chromium.org> Fixes: 25faf2f2e065 ("drm/msm: Show process names in gem_describe") Signed-off-by: Rob Clark <robdclark(a)chromium.org> --- drivers/gpu/drm/msm/msm_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 02b9ae65a96a..a4f61972667b 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -926,6 +926,7 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m, get_pid_task(aspace->pid, PIDTYPE_PID); if (task) { comm = kstrdup(task->comm, GFP_KERNEL); + put_task_struct(task); } else { comm = NULL; } -- 2.35.1

1 0

[PATCH 0/6] Allow drm_writeback_connector to accept pointer to drm_encoder
by Abhinav Kumar 17 Mar '22

17 Mar '22

There are some vendor drivers for which the writeback encoder shares hardware resources such as clocks and interrupts with the rest of the display pipeline. In addition, there can be use-cases where the writeback encoder could be a shared encoder between the physical display path and the writeback path. To accommodate for such cases, change the drm_writeback_connector to accept a pointer to drm_encoder. For existing users of drm_writeback_connector there will not be any change in functionality due to this change. This approach was first posted by Suraj Kandpal here [1] for both encoder and connector. But after discussions [2], the consensus was reached to split this change for the drm_encoder first and the drm_connector part can be reworked in a subsequent change later. Validation of this change was done using igt_writeback tests on MSM based RB5 board using the changes posted here [3]. For all other chipsets, these changes were compile-tested. [1] https://patchwork.kernel.org/project/dri-devel/patch/20220202081702.22119-1… [2] https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6… [3] https://patchwork.freedesktop.org/series/99724/ Abhinav Kumar (6): drm: allow real encoder to be passed for drm_writeback_connector drm/komeda: use drm_encoder pointer for drm_writeback_connector drm/vkms: use drm_encoder pointer for drm_writeback_connector drm/vc4: use drm_encoder pointer for drm_writeback_connector drm/rcar_du: use drm_encoder pointer for drm_writeback_connector drm/malidp: use drm_encoder pointer for drm_writeback_connector drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c | 4 +++- drivers/gpu/drm/arm/malidp_mw.c | 3 ++- drivers/gpu/drm/drm_writeback.c | 8 ++++---- drivers/gpu/drm/rcar-du/rcar_du_writeback.c | 3 ++- drivers/gpu/drm/vc4/vc4_txp.c | 14 ++++++++++---- drivers/gpu/drm/vkms/vkms_writeback.c | 4 +++- include/drm/drm_writeback.h | 13 +++++++++++-- 7 files changed, 35 insertions(+), 14 deletions(-) -- 2.7.4

4 16

[PATCH v2 1/2] drm/i915/dg2: Add preemption changes for Wa_14015141709
by Matt Roper 17 Mar '22

17 Mar '22

From: Akeem G Abodunrin <akeem.g.abodunrin(a)intel.com> Starting with DG2, preemption can no longer be controlled using userspace on a per-context basis. Instead, the hardware only allows us to enable or disable preemption in a global, system-wide basis. Also, we lose the ability to specify the preemption granularity (such as batch-level vs command-level vs object-level). v2 (MattR): - Move debugfs interface to a separate patch. (Jani) Cc: Matt Roper <matthew.d.roper(a)intel.com> Cc: Prathap Kumar Valsan <prathap.kumar.valsan(a)intel.com> Cc: John Harrison <john.c.harrison(a)intel.com> Cc: Joonas Lahtinen <joonas.lahtinen(a)linux.intel.com> Cc: Jani Nikula <jani.nikula(a)linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin(a)linux.intel.com> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin(a)intel.com> Signed-off-by: Matt Roper <matthew.d.roper(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index beca8735bae5..f695a9c96c8d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2310,7 +2310,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) FF_DOP_CLOCK_GATE_DISABLE); } - if (IS_GRAPHICS_VER(i915, 9, 12)) { + if (HAS_PERCTX_PREEMPT_CTRL(i915)) { /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ wa_masked_en(wal, GEN7_FF_SLICE_CS_CHICKEN1, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 943267393ecb..afefb3bd2714 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1396,6 +1396,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_GUC_DEPRIVILEGE(dev_priv) \ (INTEL_INFO(dev_priv)->has_guc_deprivilege) +#define HAS_PERCTX_PREEMPT_CTRL(i915) \ + ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) + static inline bool run_as_guest(void) { return !hypervisor_is_type(X86_HYPER_NATIVE); -- 2.34.1

3 3

[PATCH v2 0/3] drm/msm: Add comm/cmdline override
by Rob Clark 17 Mar '22

17 Mar '22

From: Rob Clark <robdclark(a)chromium.org> Add a way to override comm/cmdline per-drm_file. This is useful for VM scenarios where the host process is just a proxy for the actual guest process. Rob Clark (3): drm/msm: Add support for pointer params drm/msm: Split out helper to get comm/cmdline drm/msm: Add a way to override processes comm/cmdline drivers/gpu/drm/msm/adreno/adreno_gpu.c | 49 ++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 4 +- drivers/gpu/drm/msm/msm_drv.c | 8 ++-- drivers/gpu/drm/msm/msm_gpu.c | 40 ++++++++++++-------- drivers/gpu/drm/msm/msm_gpu.h | 10 ++++- drivers/gpu/drm/msm/msm_rd.c | 5 ++- drivers/gpu/drm/msm/msm_submitqueue.c | 2 + include/uapi/drm/msm_drm.h | 4 ++ 8 files changed, 94 insertions(+), 28 deletions(-) -- 2.35.1

1 3

[PATCH 1/2] drm: Add missing DP DSC extended capability definitions.
by Stanislav Lisovskiy 17 Mar '22

17 Mar '22

Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy(a)intel.com> --- drivers/gpu/drm/dp/drm_dp.c | 25 +++++++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 ++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index 703972ae14c6..fe9c72055638 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], } EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); +/** + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision + * which DP DSC sink device supports. + */ +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; + + switch (bpp_increment_dpcd) { + case DP_DSC_BITS_PER_PIXEL_1_16: + return 16; + case DP_DSC_BITS_PER_PIXEL_1_8: + return 8; + case DP_DSC_BITS_PER_PIXEL_1_4: + return 4; + case DP_DSC_BITS_PER_PIXEL_1_2: + return 2; + case DP_DSC_BITS_PER_PIXEL_1_1: + return 1; + } + + return 0; +} + + /** * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits * @dsc_dpcd: DSC capabilities from DPCD diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 51e02cf75277..e4c9f4438ccb 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -246,6 +246,9 @@ struct drm_panel; #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -284,12 +287,15 @@ struct drm_panel; #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -351,11 +357,13 @@ struct drm_panel; # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], u8 dsc_bpc[3]); +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); static inline bool drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -- 2.24.1.485.gad05a3d8e5

1 0

[PATCH v3 0/5] drm/msm: rework MDSS drivers
by Dmitry Baryshkov 17 Mar '22

17 Mar '22

These patches coninue work started by AngeloGioacchino Del Regno in the previous cycle by further decoupling and dissecting MDSS and MDP drivers probe/binding paths. This removes code duplication between MDP5 and DPU1 MDSS drivers, by merging them and moving to the top level. This patchset depends on the patches 1 and 2 from [1] Changes since v2: - Rebased on top of current msm/msm-next(-staging) - Allow disabling MDP4/MDP5/DPU/HDMI components (like we do for DP and DSI) - Made mdp5_mdss_parse_clock() static - Changed mdp5 to is_mdp5 argument in several functions - Dropped boolean device data from the mdss driver - Reworked error handling in msm_pdev_probe() - Removed unused header inclusion - Dropped __init/__exit from function prototypes Changes since v1: - Rebased on top of [2] and [1] [1] https://patchwork.freedesktop.org/series/99066/ [2] https://patchwork.freedesktop.org/series/98521/ Dmitry Baryshkov (5): drm/msm: unify MDSS drivers drm/msm: remove extra indirection for msm_mdss drm/msm: split the main platform driver drm/msm: stop using device's match data pointer drm/msm: allow runtime selection of driver components drivers/gpu/drm/msm/Kconfig | 50 ++- drivers/gpu/drm/msm/Makefile | 19 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 260 ------------- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 68 +++- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 11 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 252 ------------- drivers/gpu/drm/msm/msm_drv.c | 263 +++---------- drivers/gpu/drm/msm/msm_drv.h | 57 ++- drivers/gpu/drm/msm/msm_kms.h | 18 - drivers/gpu/drm/msm/msm_mdss.c | 429 ++++++++++++++++++++++ 11 files changed, 667 insertions(+), 770 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c delete mode 100644 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c create mode 100644 drivers/gpu/drm/msm/msm_mdss.c base-commit: 8ddb80c5fcf455fe38156636126a83eadacfb743 -- 2.34.1

4 20

RE: amd-gfx Digest, Vol 70, Issue 199
by Yat Sin, David 17 Mar '22

17 Mar '22

> > Use proper amdgpu_gem_prime_import function to handle all kinds of > imports. Remember the dmabuf reference to enable proper multi-GPU > attachment to multiple VMs without erroneously re-exporting the underlying > BO multiple times. > > Signed-off-by: Felix Kuehling <Felix.Kuehling(a)amd.com> > --- > .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 38 ++++++++++-------- > - > 1 file changed, 21 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > index cd89d2e46852..2ac61a1e665e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > @@ -2033,30 +2033,27 @@ int > amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, > struct amdgpu_bo *bo; > int ret; > > - if (dma_buf->ops != &amdgpu_dmabuf_ops) > - /* Can't handle non-graphics buffers */ > - return -EINVAL; > - > - obj = dma_buf->priv; > - if (drm_to_adev(obj->dev) != adev) > - /* Can't handle buffers from other devices */ > - return -EINVAL; > + obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf); > + if (IS_ERR(obj)) > + return PTR_ERR(obj); > > bo = gem_to_amdgpu_bo(obj); > if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | > - AMDGPU_GEM_DOMAIN_GTT))) > + AMDGPU_GEM_DOMAIN_GTT))) { > /* Only VRAM and GTT BOs are supported */ > - return -EINVAL; > + ret = -EINVAL; > + goto err_put_obj; > + } > > *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); > - if (!*mem) > - return -ENOMEM; > + if (!*mem) { > + ret = -ENOMEM; > + goto err_put_obj; > + } > > ret = drm_vma_node_allow(&obj->vma_node, drm_priv); > - if (ret) { > - kfree(mem); > - return ret; > - } > + if (ret) > + goto err_free_mem; > > if (size) > *size = amdgpu_bo_size(bo); > @@ -2073,7 +2070,8 @@ int > amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, > | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE > | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; > > - drm_gem_object_get(&bo->tbo.base); > + get_dma_buf(dma_buf); > + (*mem)->dmabuf = dma_buf; > (*mem)->bo = bo; > (*mem)->va = va; > (*mem)->domain = (bo->preferred_domains & > AMDGPU_GEM_DOMAIN_VRAM) ? > @@ -2085,6 +2083,12 @@ int > amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, > (*mem)->is_imported = true; > > return 0; > + > +err_free_mem: > + kfree(mem); Should be kfree(*mem) Regards, David > +err_put_obj: > + drm_gem_object_put(obj); > + return ret; > } > > /* Evict a userptr BO by stopping the queues if necessary

2 1

[PATCH] drm/vc4: add tracepoints for CL submissions
by Melissa Wen 17 Mar '22

17 Mar '22

Trace submit_cl_ioctl and related IRQs for CL submission and bin/render jobs execution. It might be helpful to get a rendering timeline and track job throttling. Signed-off-by: Melissa Wen <mwen(a)igalia.com> --- drivers/gpu/drm/vc4/vc4_gem.c | 7 +++ drivers/gpu/drm/vc4/vc4_irq.c | 5 ++ drivers/gpu/drm/vc4/vc4_trace.h | 95 +++++++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c index 445d3bab89e0..4abf10b66fe8 100644 --- a/drivers/gpu/drm/vc4/vc4_gem.c +++ b/drivers/gpu/drm/vc4/vc4_gem.c @@ -485,6 +485,8 @@ vc4_submit_next_bin_job(struct drm_device *dev) * immediately move it to the to-be-rendered queue. */ if (exec->ct0ca != exec->ct0ea) { + trace_vc4_submit_cl(dev, false, exec->seqno, exec->ct0ca, + exec->ct0ea); submit_cl(dev, 0, exec->ct0ca, exec->ct0ea); } else { struct vc4_exec_info *next; @@ -519,6 +521,7 @@ vc4_submit_next_render_job(struct drm_device *dev) */ vc4_flush_texture_caches(dev); + trace_vc4_submit_cl(dev, true, exec->seqno, exec->ct1ca, exec->ct1ea); submit_cl(dev, 1, exec->ct1ca, exec->ct1ea); } @@ -1135,6 +1138,10 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data, struct dma_fence *in_fence; int ret = 0; + trace_vc4_submit_cl_ioctl(dev, args->bin_cl_size, + args->shader_rec_size, + args->bo_handle_count); + if (!vc4->v3d) { DRM_DEBUG("VC4_SUBMIT_CL with no VC4 V3D probed\n"); return -ENODEV; diff --git a/drivers/gpu/drm/vc4/vc4_irq.c b/drivers/gpu/drm/vc4/vc4_irq.c index 20fa8e34c20b..4342fb43e8c1 100644 --- a/drivers/gpu/drm/vc4/vc4_irq.c +++ b/drivers/gpu/drm/vc4/vc4_irq.c @@ -51,6 +51,7 @@ #include "vc4_drv.h" #include "vc4_regs.h" +#include "vc4_trace.h" #define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \ V3D_INT_FLDONE | \ @@ -123,6 +124,8 @@ vc4_irq_finish_bin_job(struct drm_device *dev) if (!exec) return; + trace_vc4_bcl_end_irq(dev, exec->seqno); + vc4_move_job_to_render(dev, exec); next = vc4_first_bin_job(vc4); @@ -161,6 +164,8 @@ vc4_irq_finish_render_job(struct drm_device *dev) if (!exec) return; + trace_vc4_rcl_end_irq(dev, exec->seqno); + vc4->finished_seqno++; list_move_tail(&exec->head, &vc4->job_done_list); diff --git a/drivers/gpu/drm/vc4/vc4_trace.h b/drivers/gpu/drm/vc4/vc4_trace.h index 1cccde0b09a7..7f4c49e7e011 100644 --- a/drivers/gpu/drm/vc4/vc4_trace.h +++ b/drivers/gpu/drm/vc4/vc4_trace.h @@ -52,6 +52,101 @@ TRACE_EVENT(vc4_wait_for_seqno_end, __entry->dev, __entry->seqno) ); +TRACE_EVENT(vc4_submit_cl_ioctl, + TP_PROTO(struct drm_device *dev, u32 bin_cl_size, u32 shader_rec_size, u32 bo_count), + TP_ARGS(dev, bin_cl_size, shader_rec_size, bo_count), + + TP_STRUCT__entry( + __field(u32, dev) + __field(u32, bin_cl_size) + __field(u32, shader_rec_size) + __field(u32, bo_count) + ), + + TP_fast_assign( + __entry->dev = dev->primary->index; + __entry->bin_cl_size = bin_cl_size; + __entry->shader_rec_size = shader_rec_size; + __entry->bo_count = bo_count; + ), + + TP_printk("dev=%u, bin_cl_size=%u, shader_rec_size=%u, bo_count=%u", + __entry->dev, + __entry->bin_cl_size, + __entry->shader_rec_size, + __entry->bo_count) +); + +TRACE_EVENT(vc4_submit_cl, + TP_PROTO(struct drm_device *dev, bool is_render, + uint64_t seqno, + u32 ctnqba, u32 ctnqea), + TP_ARGS(dev, is_render, seqno, ctnqba, ctnqea), + + TP_STRUCT__entry( + __field(u32, dev) + __field(bool, is_render) + __field(u64, seqno) + __field(u32, ctnqba) + __field(u32, ctnqea) + ), + + TP_fast_assign( + __entry->dev = dev->primary->index; + __entry->is_render = is_render; + __entry->seqno = seqno; + __entry->ctnqba = ctnqba; + __entry->ctnqea = ctnqea; + ), + + TP_printk("dev=%u, %s, seqno=%llu, 0x%08x..0x%08x", + __entry->dev, + __entry->is_render ? "RCL" : "BCL", + __entry->seqno, + __entry->ctnqba, + __entry->ctnqea) +); + +TRACE_EVENT(vc4_bcl_end_irq, + TP_PROTO(struct drm_device *dev, + uint64_t seqno), + TP_ARGS(dev, seqno), + + TP_STRUCT__entry( + __field(u32, dev) + __field(u64, seqno) + ), + + TP_fast_assign( + __entry->dev = dev->primary->index; + __entry->seqno = seqno; + ), + + TP_printk("dev=%u, seqno=%llu", + __entry->dev, + __entry->seqno) +); + +TRACE_EVENT(vc4_rcl_end_irq, + TP_PROTO(struct drm_device *dev, + uint64_t seqno), + TP_ARGS(dev, seqno), + + TP_STRUCT__entry( + __field(u32, dev) + __field(u64, seqno) + ), + + TP_fast_assign( + __entry->dev = dev->primary->index; + __entry->seqno = seqno; + ), + + TP_printk("dev=%u, seqno=%llu", + __entry->dev, + __entry->seqno) +); + #endif /* _VC4_TRACE_H_ */ /* This part must be outside protection */ -- 2.34.1

3 6

[PATCH 1/2] drm/i915: Fix renamed struct field
by Lucas De Marchi 17 Mar '22

17 Mar '22

Earlier versions of commit a5b7ef27da60 ("drm/i915: Add struct to hold IP version") named "ver" as "arch" and then when it was renamed it missed the rename on MEDIA_VER_FULL() since it it's currently not used. Fixes: a5b7ef27da60 ("drm/i915: Add struct to hold IP version") Cc: José Roberto de Souza <jose.souza(a)intel.com> Cc: Matt Roper <matthew.d.roper(a)intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi(a)intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 26df561a4e94..7458b107a1d6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -922,7 +922,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) #define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver) -#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.arch, \ +#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.ver, \ INTEL_INFO(i915)->media.rel) #define IS_MEDIA_VER(i915, from, until) \ (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) -- 2.35.1

3 4

[PATCH v1 0/3] split vm_normal_pages for LRU and non-LRU handling
by Alex Sierra 17 Mar '22

17 Mar '22

DEVICE_COHERENT pages introduce a subtle distinction in the way "normal" pages can be used by various callers throughout the kernel. They behave like normal pages for purposes of mapping in CPU page tables, and for COW. But they do not support LRU lists, NUMA migration or THP. Therefore we split vm_normal_page into two functions vm_normal_any_page and vm_normal_lru_page. The latter will only return pages that can be put on an LRU list and that support NUMA migration, KSM and THP. HMM tests were added to selftest to excercise these changes with device coherent pages. New test called hmm_cow_in_device, will test pages marked as COW, allocated in device zone. Also, more configurations were added into hmm_gup_test to test basic get user pages and get user pages fast paths in device zone pages. Alex Sierra (3): mm: split vm_normal_pages for LRU and non-LRU handling tools: add more gup configs to hmm_gup selftests tools: add selftests to hmm for COW in device memory fs/proc/task_mmu.c | 12 +-- include/linux/mm.h | 11 +- mm/gup.c | 10 +- mm/hmm.c | 2 +- mm/huge_memory.c | 2 +- mm/khugepaged.c | 8 +- mm/ksm.c | 4 +- mm/madvise.c | 4 +- mm/memcontrol.c | 2 +- mm/memory.c | 38 ++++--- mm/mempolicy.c | 4 +- mm/migrate.c | 2 +- mm/migrate_device.c | 2 +- mm/mlock.c | 6 +- mm/mprotect.c | 2 +- tools/testing/selftests/vm/hmm-tests.c | 139 +++++++++++++++++++++---- 16 files changed, 185 insertions(+), 63 deletions(-) -- 2.32.0

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dri-devel March 2022