dri-devel March 2022

dri-devel@lists.freedesktop.org

370 participants
780 discussions

[PATCH] drm/nouveau: Fix spelling mistake "endianess" -> "endianness"
by Colin Ian King 16 Mar '22

16 Mar '22

There is a spelling mistake in a nvdev_error error message. Fix it. Signed-off-by: Colin Ian King <colin.i.king(a)gmail.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 88d262ba648c..62efbd0f3846 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2935,7 +2935,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, /* switch mmio to cpu's native endianness */ if (!nvkm_device_endianness(device)) { nvdev_error(device, - "Couldn't switch GPU to CPUs endianess\n"); + "Couldn't switch GPU to CPUs endianness\n"); ret = -ENOSYS; goto done; } -- 2.35.1

2 1

2022 X.Org Foundation Membership deadline for voting in the election
by Lyude Paul 16 Mar '22

16 Mar '22

The 2022 X.Org Foundation elections are rapidly approaching. We will be forwarding the election schedule and nominating process to the membership shortly. Please note that only current members can vote in the upcoming election, and that the deadline for new memberships or renewals to vote in the upcoming election is 31 March 2022 at 23:59 UTC. If you are interested in joining the X.Org Foundation or in renewing your membership, please visit the membership system site at: https://members.x.org/ Lyude Paul, on behalf of the X.Org elections committee

1 0

2022 X.Org Board of Directors Elections Nomination period is NOW
by Lyude Paul 16 Mar '22

16 Mar '22

The Board consists of directors elected from the membership. Each year, an election is held to bring the total number of directors to eight. The four members receiving the highest vote totals will serve as directors for two year terms. The directors who received two year terms starting in 2021 were Lyude Paul, Samuel Iglesias Gonsálvez, Manasi D Navare and Daniel Vetter. They will continue to serve until their term ends in 2023. Current directors whose term expires in 2022 are Emma Anholt, Keith Packard, Harry Wentland and Mark Filion. A director is expected to participate in the fortnightly IRC meeting to discuss current business and to attend the annual meeting of the X.Org Foundation, which will be held at a location determined in advance by the Board of Directors. A member may nominate themselves or any other member they feel is qualified. Nominations should be sent to the Election Committee at elections at x.org. Nominees shall be required to be current members of the X.Org Foundation, and submit a personal statement of up to 200 words that will be provided to prospective voters. The collected statements, along with the statement of contribution to the X.Org Foundation in the member's account page on http://members.x.org, will be made available to all voters to help them make their voting decisions. Nominations, membership applications or renewals and completed personal statements must be received no later than 23:59 UTC on 20th March 2022. The slate of candidates will be published 28th March 2022 and candidate Q&A will begin then. The deadline for Xorg membership applications and renewals is 31st March 2022. Cheers, Lyude Paul, on behalf of the X.Org BoD

1 0

[PATCH v2 00/12] drm/gma500: Various cleanups to GEM code
by Thomas Zimmermann 16 Mar '22

16 Mar '22

Refactor and simplify various parts of the memory management. This includes locking, initialization and finalizer functions, and code organization. Tested on Atom N2800 hardware. v2: * put common code in psb_gtt_{init,fini,resume}() into helpers (Sam, Patrik) Thomas Zimmermann (12): drm/gma500: Remove struct psb_gem_object.npage drm/gma500: Acquire reservation lock for GEM objects drm/gma500: Move GTT locking into GTT helpers drm/gma500: Remove struct psb_gtt.sem sempahore drm/gma500: Move GTT setup and restoration into helper funtions drm/gma500: Move GTT resume logic out of psb_gtt_init() drm/gma500: Cleanup GTT uninit and error handling drm/gma500: Split GTT init/resume/fini into GTT and GEM functions drm/gma500: Inline psb_gtt_restore() drm/gma500: Move GEM memory management functions to gem.c drm/gma500: Move GTT enable and disable code into helpers drm/gma500: Move GTT memory-range setup into helper drivers/gpu/drm/gma500/gem.c | 161 ++++++++++++++- drivers/gpu/drm/gma500/gem.h | 13 +- drivers/gpu/drm/gma500/gma_display.c | 8 +- drivers/gpu/drm/gma500/gtt.c | 295 +++++++++++++-------------- drivers/gpu/drm/gma500/gtt.h | 8 +- drivers/gpu/drm/gma500/power.c | 5 +- drivers/gpu/drm/gma500/psb_drv.c | 13 +- drivers/gpu/drm/gma500/psb_drv.h | 1 - 8 files changed, 317 insertions(+), 187 deletions(-) base-commit: 710a019ad85e96e66f7d75ee7f4733cdd8a2b0d0 prerequisite-patch-id: c2b2f08f0eccc9f5df0c0da49fa1d36267deb11d prerequisite-patch-id: c67e5d886a47b7d0266d81100837557fda34cb24 prerequisite-patch-id: 6e1032c6302461624f33194c8b8f37103a3fa6ef -- 2.35.1

2 16

[PATCH] drm/i915: avoid concurrent writes to aux_inv
by fei.yang＠intel.com 16 Mar '22

16 Mar '22

From: Fei Yang <fei.yang(a)intel.com> GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the rq->engine is not necessarily the engine eventually carrying out the request, and potentially the engine could even be a virtual one (with engine->instance being -1). With this patch, auxiliary table invalidation is done only for the engine executing the request. And the mmio address for the aux_inv register is set after the engine instance becomes certain. Signed-off-by: Chris Wilson <chris.p.wilson(a)intel.com> Signed-off-by: Fei Yang <fei.yang(a)intel.com> --- drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 9 +++ drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 9 +++ drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 61 ++++++++----------- .../drm/i915/gt/intel_execlists_submission.c | 35 +++++++++++ drivers/gpu/drm/i915/i915_request.h | 2 + 5 files changed, 82 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c index 1c82caf525c3..0ec4986e4805 100644 --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c @@ -37,6 +37,9 @@ int gen2_emit_flush(struct i915_request *rq, u32 mode) intel_ring_advance(rq, cs); + /* hsdes: 1809175790. No fixup needed for gen2 */ + rq->aux_inv_fixup = NULL; + return 0; } @@ -123,6 +126,9 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode) intel_ring_advance(rq, cs); + /* hsdes: 1809175790. No fixup needed for gen4 rcs */ + rq->aux_inv_fixup = NULL; + return 0; } @@ -138,6 +144,9 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) *cs++ = MI_NOOP; intel_ring_advance(rq, cs); + /* hsdes: 1809175790. No fixup needed for gen4 vcs */ + rq->aux_inv_fixup = NULL; + return 0; } diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c index 5e65550b4dfb..efe51c4662fe 100644 --- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c @@ -137,6 +137,9 @@ int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode) *cs++ = 0; intel_ring_advance(rq, cs); + /* hsdes: 1809175790. No fixup needed for gen6 */ + rq->aux_inv_fixup = NULL; + return 0; } @@ -208,6 +211,9 @@ static int mi_flush_dw(struct i915_request *rq, u32 flags) intel_ring_advance(rq, cs); + /* hsdes: 1809175790. No fixup needed for gen6 */ + rq->aux_inv_fixup = NULL; + return 0; } @@ -347,6 +353,9 @@ int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode) *cs++ = 0; intel_ring_advance(rq, cs); + /* hsdes: 1809175790. No fixup needed for gen7 rcs */ + rq->aux_inv_fixup = NULL; + return 0; } diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index b1b9c3fd7bf9..b6374cf53314 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -73,6 +73,9 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode) intel_ring_advance(rq, cs); + /* hsdes: 1809175790. No fixup needed for gen8 rcs */ + rq->aux_inv_fixup = NULL; + return 0; } @@ -106,6 +109,9 @@ int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode) *cs++ = 0; /* value */ intel_ring_advance(rq, cs); + /* hsdes: 1809175790. No fixup needed for gen8 xcs */ + rq->aux_inv_fixup = NULL; + return 0; } @@ -157,6 +163,9 @@ int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode) intel_ring_advance(rq, cs); } + /* hsdes: 1809175790. No fixup needed for gen11 rcs */ + rq->aux_inv_fixup = NULL; + return 0; } @@ -165,30 +174,6 @@ static u32 preparser_disable(bool state) return MI_ARB_CHECK | 1 << 8 | state; } -static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine) -{ - static const i915_reg_t vd[] = { - GEN12_VD0_AUX_NV, - GEN12_VD1_AUX_NV, - GEN12_VD2_AUX_NV, - GEN12_VD3_AUX_NV, - }; - - static const i915_reg_t ve[] = { - GEN12_VE0_AUX_NV, - GEN12_VE1_AUX_NV, - }; - - if (engine->class == VIDEO_DECODE_CLASS) - return vd[engine->instance]; - - if (engine->class == VIDEO_ENHANCEMENT_CLASS) - return ve[engine->instance]; - - GEM_BUG_ON("unknown aux_inv reg\n"); - return INVALID_MMIO_REG; -} - static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs) { *cs++ = MI_LOAD_REGISTER_IMM(1); @@ -274,6 +259,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) intel_ring_advance(rq, cs); } + /* hsdes: 1809175790. aux_inv has been done above, no fixup needed */ + rq->aux_inv_fixup = NULL; + return 0; } @@ -288,7 +276,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) if (mode & EMIT_INVALIDATE) aux_inv = rq->engine->mask & ~BIT(BCS0); if (aux_inv) - cmd += 2 * hweight32(aux_inv) + 2; + cmd += 4; cs = intel_ring_begin(rq, cmd); if (IS_ERR(cs)) @@ -319,16 +307,21 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) *cs++ = 0; /* value */ if (aux_inv) { /* hsdes: 1809175790 */ - struct intel_engine_cs *engine; - unsigned int tmp; - - *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv)); - for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) { - *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine)); - *cs++ = AUX_INV; - } + /* + * We don't know which engine will eventually carry out + * this request, so the mmio aux_inv register address is + * unknown at this moment. We save the cs pointer supposed + * to hold the aux_inv address in rq->aux_inv_fixup and set + * it in execlists_dequeue() when the engine instance + * carrying out this request becomes certain + */ + *cs++ = MI_LOAD_REGISTER_IMM(1); + rq->aux_inv_fixup = cs; /* save the pointer to aux_inv */ + *cs++ = 0; /* mmio addr to be set at submission to HW */ + *cs++ = AUX_INV; *cs++ = MI_NOOP; - } + } else + rq->aux_inv_fixup = NULL; if (mode & EMIT_INVALIDATE) *cs++ = preparser_disable(false); diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index e1470bb60f34..7e8552414275 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1258,6 +1258,34 @@ static bool completed(const struct i915_request *rq) return __i915_request_is_complete(rq); } +static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine) +{ + static const i915_reg_t vd[] = { + GEN12_VD0_AUX_NV, + GEN12_VD1_AUX_NV, + GEN12_VD2_AUX_NV, + GEN12_VD3_AUX_NV, + }; + + static const i915_reg_t ve[] = { + GEN12_VE0_AUX_NV, + GEN12_VE1_AUX_NV, + }; + + if (engine->class == VIDEO_DECODE_CLASS) { + GEM_BUG_ON(engine->instance >= ARRAY_SIZE(vd)); + return vd[engine->instance]; + } + + if (engine->class == VIDEO_ENHANCEMENT_CLASS) { + GEM_BUG_ON(engine->instance >= ARRAY_SIZE(ve)); + return ve[engine->instance]; + } + + GEM_BUG_ON("unknown aux_inv reg\n"); + return INVALID_MMIO_REG; +} + static void execlists_dequeue(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; @@ -1538,6 +1566,13 @@ static void execlists_dequeue(struct intel_engine_cs *engine) } if (__i915_request_submit(rq)) { + /* hsdes: 1809175790 */ + if (rq->aux_inv_fixup) { + *rq->aux_inv_fixup = + i915_mmio_reg_offset + (aux_inv_reg(engine)); + rq->execution_mask = engine->mask; + } if (!merge) { *port++ = i915_request_get(last); last = NULL; diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h index 28b1f9db5487..8e0764c43936 100644 --- a/drivers/gpu/drm/i915/i915_request.h +++ b/drivers/gpu/drm/i915/i915_request.h @@ -312,6 +312,8 @@ struct i915_request { struct i915_capture_list *capture_list; #endif + u32 *aux_inv_fixup; /* hsdes: 1809175790 */ + /** Time at which this request was emitted, in jiffies. */ unsigned long emitted_jiffies; -- 2.25.1

4 5

[PATCH v2 1/2] staging: fbtft: Constify buf parameter in fbtft_dbg_hex()
by Andy Shevchenko 16 Mar '22

16 Mar '22

It's obvious that we don't and shouldn't modify buffer that is about to be dumped. Constify parameter in fbtft_dbg_hex() to make it clear. Fixes: c296d5f9957c ("staging: fbtft: core support") Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- v2: new patch to fix a warning (Greg) drivers/staging/fbtft/fbtft-core.c | 2 +- drivers/staging/fbtft/fbtft.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/fbtft/fbtft-core.c b/drivers/staging/fbtft/fbtft-core.c index f2684d2d6851..6dc77895a87c 100644 --- a/drivers/staging/fbtft/fbtft-core.c +++ b/drivers/staging/fbtft/fbtft-core.c @@ -49,7 +49,7 @@ int fbtft_write_buf_dc(struct fbtft_par *par, void *buf, size_t len, int dc) EXPORT_SYMBOL(fbtft_write_buf_dc); void fbtft_dbg_hex(const struct device *dev, int groupsize, - void *buf, size_t len, const char *fmt, ...) + const void *buf, size_t len, const char *fmt, ...) { va_list args; static char textbuf[512]; diff --git a/drivers/staging/fbtft/fbtft.h b/drivers/staging/fbtft/fbtft.h index 55677efc0138..c3d8b2aae607 100644 --- a/drivers/staging/fbtft/fbtft.h +++ b/drivers/staging/fbtft/fbtft.h @@ -240,7 +240,7 @@ struct fbtft_par { int fbtft_write_buf_dc(struct fbtft_par *par, void *buf, size_t len, int dc); __printf(5, 6) void fbtft_dbg_hex(const struct device *dev, int groupsize, - void *buf, size_t len, const char *fmt, ...); + const void *buf, size_t len, const char *fmt, ...); struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display, struct device *dev, struct fbtft_platform_data *pdata); -- 2.35.1

1 1

[PATCH v1 1/1] staging: fbtft: Consider type of init sequence values in fbtft_init_display()
by Andy Shevchenko 16 Mar '22

16 Mar '22

In the fbtft_init_display() the init sequence is printed for the debug purposes. Unfortunately the current code doesn't take into account that values in the buffer are of the s16 type. Consider that and replace the printing code with fbtft_par_dbg_hex() call. Fixes: b888897014a9 ("staging/fbtft: Remove all strcpy() uses") Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- drivers/staging/fbtft/fbtft-core.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/staging/fbtft/fbtft-core.c b/drivers/staging/fbtft/fbtft-core.c index 4a35347b3020..b28a059ad3b4 100644 --- a/drivers/staging/fbtft/fbtft-core.c +++ b/drivers/staging/fbtft/fbtft-core.c @@ -1035,10 +1035,9 @@ int fbtft_init_display(struct fbtft_par *par) for (j = 0; par->init_sequence[i + 1 + j] >= 0; j++) ; - fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, - "init: write(0x%02X) %*ph\n", - par->init_sequence[i], j, - &par->init_sequence[i + 1]); + fbtft_par_dbg_hex(DEBUG_INIT_DISPLAY, par, par->info->device, + s16, &par->init_sequence[i + 1], j, + "init: write(0x%02X)", par->init_sequence[i]); /* Write */ j = 0; -- 2.34.1

2 5

[PATCH v2 0/6] Allow drm_writeback_connector to accept pointer to drm_encoder
by Abhinav Kumar 16 Mar '22

16 Mar '22

There are some vendor drivers for which the writeback encoder shares hardware resources such as clocks and interrupts with the rest of the display pipeline. In addition, there can be use-cases where the writeback encoder could be a shared encoder between the physical display path and the writeback path. To accommodate for such cases, change the drm_writeback_connector to accept a pointer to drm_encoder. For existing users of drm_writeback_connector there will not be any change in functionality due to this change. This approach was first posted by Suraj Kandpal here [1] for both encoder and connector. But after discussions [2], the consensus was reached to split this change for the drm_encoder first and the drm_connector part can be reworked in a subsequent change later. Validation of this change was done using igt_writeback tests on MSM based RB5 board using the changes posted here [3]. For all other chipsets, these changes were compile-tested. [1] https://patchwork.kernel.org/project/dri-devel/patch/20220202081702.22119-1… [2] https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6… [3] https://patchwork.freedesktop.org/series/99724/ changes in v2: - introduce a new API drm_writeback_connector_init_with_encoder() - allow passing possible_crtcs for existing users of drm_writeback_connector_init() Abhinav Kumar (6): drm: allow real encoder to be passed for drm_writeback_connector drm/komeda: pass possible_crtcs as parameter for drm_writeback_connector drm/vkms: pass possible_crtcs as parameter for drm_writeback_connector drm/vc4: change vc4 driver to use drm_writeback_connector_init_with_encoder() drm/rcar_du: pass possible_crtcs as parameter for drm_writeback_connector drm/malidp: pass possible_crtcs as parameter for drm_writeback_connector .../drm/arm/display/komeda/komeda_wb_connector.c | 3 +- drivers/gpu/drm/arm/malidp_mw.c | 5 +- drivers/gpu/drm/drm_writeback.c | 144 +++++++++++++++------ drivers/gpu/drm/rcar-du/rcar_du_writeback.c | 5 +- drivers/gpu/drm/vc4/vc4_txp.c | 30 ++++- drivers/gpu/drm/vkms/vkms_writeback.c | 3 +- include/drm/drm_writeback.h | 27 +++- 7 files changed, 161 insertions(+), 56 deletions(-) -- 2.7.4

2 8

[PATCH 1/2] drm: mediatek: mtk_drm_plane: Use kmalloc in mtk_plane_duplicate_state
by AngeloGioacchino Del Regno 16 Mar '22

16 Mar '22

There is no need to zero out the newly allocated memory because we are duplicating all members of struct mtk_plane_state: switch to kmalloc to save some overhead. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno(a)collabora.com> --- drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index c74cb94e445e..39cb9a80d976 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -57,7 +57,7 @@ static struct drm_plane_state *mtk_plane_duplicate_state(struct drm_plane *plane struct mtk_plane_state *old_state = to_mtk_plane_state(plane->state); struct mtk_plane_state *state; - state = kzalloc(sizeof(*state), GFP_KERNEL); + state = kmalloc(sizeof(*state), GFP_KERNEL); if (!state) return NULL; -- 2.33.1

2 5

[PATCH 0/3] Move FPU related code from DCN3.1x drivers to DML folder
by Melissa Wen 16 Mar '22

16 Mar '22

This series moves FPU code from DCN 3.1x drivers to dml/dcn31 folder to isolate FPU operations. For this, it creates dcn31_fpu files to centralize FPU operations and structs from dcn31x drivers, that include: - _vcs_dpi_ip_params_st and _vcs_dpi_soc_bounding_box_st structs - dcn31x_update_bw_bounding_box() functions - dcn31_calculate_wm_and_dlg_fp() Also, it adds dc_assert_fp_enabled() in public dml-fpu functions, as required, and I've checked if their calls are properly wrapped by DC_FP_START/END (and removed when inside dml/fpu files too). Melissa Wen (3): drm/amd/dicplay: move FPU related code from dcn31 to dml/dcn31 folder drm/amd/display: move FPU related code from dcn315 to dml/dcn31 folder drm/amd/display: move FPU related code from dcn316 to dml/dcn31 folder drivers/gpu/drm/amd/display/dc/dcn31/Makefile | 26 - .../drm/amd/display/dc/dcn31/dcn31_resource.c | 355 +------ .../drm/amd/display/dc/dcn31/dcn31_resource.h | 4 +- .../gpu/drm/amd/display/dc/dcn315/Makefile | 26 - .../amd/display/dc/dcn315/dcn315_resource.c | 232 +---- .../amd/display/dc/dcn315/dcn315_resource.h | 3 + .../gpu/drm/amd/display/dc/dcn316/Makefile | 26 - .../amd/display/dc/dcn316/dcn316_resource.c | 231 +---- .../amd/display/dc/dcn316/dcn316_resource.h | 3 + drivers/gpu/drm/amd/display/dc/dml/Makefile | 2 + .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 863 ++++++++++++++++++ .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.h | 44 + 12 files changed, 921 insertions(+), 894 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h -- 2.34.1

2 4

← Newer
1
...
44
45
46
47
48
49
50
...
78
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel March 2022