dri-devel March 2022

dri-devel@lists.freedesktop.org

370 participants
780 discussions

[PATCH v2 2/2] drm: rcar-du: Add RZ/G2L DSI driver
by Biju Das 18 Apr '22

18 Apr '22

This driver supports the MIPI DSI encoder found in the RZ/G2L SoC. It currently supports DSI mode only. Signed-off-by: Biju Das <biju.das.jz(a)bp.renesas.com> --- v1->v2: * Rework based on dt-binding change (DSI + D-PHY) as single block * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write and rzg2l_mipi_dsi_link_write * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read RFC->v1: * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG and dropped DRM as it is implied by DRM_BRIDGE * Used devm_reset_control_get_exclusive() for reset handle * Removed bool hsclkmode from struct rzg2l_mipi_dsi * Added error check for pm, using pm_runtime_resume_and_get() instead of pm_runtime_get_sync() * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach() * Avoided read-modify-write stopping hsclock * Used devm_platform_ioremap_resource for resource allocation * Removed unnecessary assert call from probe and remove. * wrap the line after the PTR_ERR() in probe() * Updated reset failure messages in probe * Fixed the typo arstc->prstc * Made hex constants to lower case. RFC: * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612… --- drivers/gpu/drm/rcar-du/Kconfig | 8 + drivers/gpu/drm/rcar-du/Makefile | 1 + drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c | 686 ++++++++++++++++++ drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 149 ++++ 4 files changed, 844 insertions(+) create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig index e40fb0c53f9b..83d7d28214a0 100644 --- a/drivers/gpu/drm/rcar-du/Kconfig +++ b/drivers/gpu/drm/rcar-du/Kconfig @@ -64,6 +64,14 @@ config DRM_RCAR_MIPI_DSI help Enable support for the R-Car Display Unit embedded MIPI DSI encoders. +config DRM_RZG2L_MIPI_DSI + tristate "RZ/G2L MIPI DSI Encoder Support" + depends on DRM_BRIDGE && OF + depends on ARCH_RENESAS || COMPILE_TEST + select DRM_MIPI_DSI + help + Enable support for the RZ/G2L Display Unit embedded MIPI DSI encoders. + config DRM_RCAR_VSP bool "R-Car DU VSP Compositor Support" if ARM default y if ARM64 diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile index 01ba78e56b53..7fb4f8717fc4 100644 --- a/drivers/gpu/drm/rcar-du/Makefile +++ b/drivers/gpu/drm/rcar-du/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_RCAR_LVDS) += rcar_lvds.o obj-$(CONFIG_DRM_RCAR_MIPI_DSI) += rcar_mipi_dsi.o obj-$(CONFIG_DRM_RZG2L_DU) += rzg2l-du-drm.o +obj-$(CONFIG_DRM_RZG2L_MIPI_DSI) += rzg2l_mipi_dsi.o # 'remote-endpoint' is fixed up at run-time DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c new file mode 100644 index 000000000000..3b785041ba5e --- /dev/null +++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c @@ -0,0 +1,686 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L MIPI DSI Encoder Driver + * + * Copyright (C) 2022 Renesas Electronics Corporation + */ +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> +#include <linux/slab.h> + +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_of.h> +#include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> + +#include "rzg2l_mipi_dsi_regs.h" + +struct rzg2l_mipi_dsi { + struct device *dev; + void __iomem *mmio; + + struct reset_control *rstc; + struct reset_control *arstc; + struct reset_control *prstc; + + struct mipi_dsi_host host; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + + struct clk *vclk; + + enum mipi_dsi_pixel_format format; + unsigned int num_data_lanes; + unsigned int lanes; + unsigned long mode_flags; +}; + +static inline struct rzg2l_mipi_dsi * +bridge_to_rzg2l_mipi_dsi(struct drm_bridge *bridge) +{ + return container_of(bridge, struct rzg2l_mipi_dsi, bridge); +} + +static inline struct rzg2l_mipi_dsi * +host_to_rzg2l_mipi_dsi(struct mipi_dsi_host *host) +{ + return container_of(host, struct rzg2l_mipi_dsi, host); +} + +static void rzg2l_mipi_dsi_phy_write(void __iomem *mem, u32 reg, u32 data) +{ + iowrite32(data, mem + reg); +} + +static void rzg2l_mipi_dsi_link_write(void __iomem *mem, u32 reg, u32 data) +{ + iowrite32(data, mem + LINK_REG_OFFSET + reg); +} + +static u32 rzg2l_mipi_dsi_link_read(void __iomem *mem, u32 reg) +{ + return ioread32(mem + LINK_REG_OFFSET + reg); +} + +/* ----------------------------------------------------------------------------- + * Hardware Setup + */ + +static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, + const struct drm_display_mode *mode) +{ + unsigned long hsfreq; + u32 txsetr; + u32 clstptsetr; + u32 lptrnstsetr; + u8 max_num_lanes; + u32 clkkpt; + u32 clkbfht; + u32 clkstpt; + u32 golpbkt; + unsigned int bpp; + struct { + u32 tclk_miss; + u32 t_init; + u32 tclk_prepare; + u32 tclk_settle; + u32 tclk_trail; + u32 tclk_post; + u32 tclk_pre; + u32 tclk_zero; + u32 tlpx; + u32 ths_prepare; + u32 ths_settle; + u32 ths_exit; + u32 ths_trail; + u32 ths_zero; + } timings; + u32 dphyctrl0; + u32 dphytim0; + u32 dphytim1; + u32 dphytim2; + u32 dphytim3; + int ret; + + /* Relationship between hsclk and vclk must follow + * vclk * bpp = hsclk * 8 * lanes + * where vclk: video clock (Hz) + * bpp: video pixel bit depth + * hsclk: DSI HS Byte clock frequency (Hz) + * lanes: number of data lanes + * + * hsclk(bit) = hsclk(byte) * 8 + */ + + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes); + + /* Initializing DPHY before accessing LINK */ + + /* All DSI global operation timings are set with recommended setting */ + if (hsfreq > 250000) { + timings.tclk_miss = 1; + timings.t_init = 79801; + timings.tclk_prepare = 8; + timings.tclk_settle = 9; + timings.tclk_trail = 7; + timings.tclk_post = 35; + timings.tclk_pre = 4; + timings.tclk_zero = 33; + timings.tlpx = 6; + timings.ths_prepare = 9; + timings.ths_settle = 9; + timings.ths_exit = 13; + timings.ths_trail = 9; + timings.ths_zero = 16; + } else { + timings.tclk_miss = 1; + timings.t_init = 79801; + timings.tclk_prepare = 8; + timings.tclk_settle = 9; + timings.tclk_trail = 10; + timings.tclk_post = 94; + timings.tclk_pre = 13; + timings.tclk_zero = 33; + timings.tlpx = 6; + timings.ths_prepare = 12; + timings.ths_settle = 9; + timings.ths_exit = 13; + timings.ths_trail = 17; + timings.ths_zero = 23; + } + + ret = reset_control_deassert(dsi->arstc); + if (ret < 0) + return ret; + + ret = reset_control_deassert(dsi->prstc); + if (ret < 0) + return ret; + + ret = pm_runtime_resume_and_get(dsi->dev); + if (ret < 0) { + reset_control_assert(dsi->prstc); + reset_control_assert(dsi->arstc); + return ret; + } + + clk_set_rate(dsi->vclk, mode->clock * 1000); + + dphyctrl0 = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN | + DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR; + + rzg2l_mipi_dsi_phy_write(dsi->mmio, DSIDPHYCTRL0, dphyctrl0); + usleep_range(20, 30); + + dphyctrl0 |= DSIDPHYCTRL0_EN_LDO1200; + rzg2l_mipi_dsi_phy_write(dsi->mmio, DSIDPHYCTRL0, dphyctrl0); + usleep_range(10, 20); + + dphytim0 = DSIDPHYTIM0_TCLK_MISS(timings.tclk_miss) | + DSIDPHYTIM0_T_INIT(timings.t_init); + dphytim1 = DSIDPHYTIM1_THS_PREPARE(timings.ths_prepare) | + DSIDPHYTIM1_TCLK_PREPARE(timings.tclk_prepare) | + DSIDPHYTIM1_THS_SETTLE(timings.ths_settle) | + DSIDPHYTIM1_TCLK_SETTLE(timings.tclk_settle); + dphytim2 = DSIDPHYTIM2_TCLK_TRAIL(timings.tclk_trail) | + DSIDPHYTIM2_TCLK_POST(timings.tclk_post) | + DSIDPHYTIM2_TCLK_PRE(timings.tclk_pre) | + DSIDPHYTIM2_TCLK_ZERO(timings.tclk_zero); + dphytim3 = DSIDPHYTIM3_TLPX(timings.tlpx) | + DSIDPHYTIM3_THS_EXIT(timings.ths_exit) | + DSIDPHYTIM3_THS_TRAIL(timings.ths_trail) | + DSIDPHYTIM3_THS_ZERO(timings.ths_zero); + + rzg2l_mipi_dsi_phy_write(dsi->mmio, DSIDPHYTIM0, dphytim0); + rzg2l_mipi_dsi_phy_write(dsi->mmio, DSIDPHYTIM1, dphytim1); + rzg2l_mipi_dsi_phy_write(dsi->mmio, DSIDPHYTIM2, dphytim2); + rzg2l_mipi_dsi_phy_write(dsi->mmio, DSIDPHYTIM3, dphytim3); + + reset_control_deassert(dsi->rstc); + udelay(1); + + /* Check number of lanes capability */ + max_num_lanes = rzg2l_mipi_dsi_link_read(dsi->mmio, TXSETR) >> 16; + max_num_lanes = (max_num_lanes & 0x3) + 1; + if (max_num_lanes < dsi->lanes) { + dev_err(dsi->dev, "DPHY can not support %d lanes", dsi->lanes); + return -EINVAL; + } + + /* Enable Data lanes and Clock lanes */ + txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; + rzg2l_mipi_dsi_link_write(dsi->mmio, TXSETR, txsetr); + + /* + * Global timings characteristic depends on high speed Clock Frequency + * Currently MIPI DSI-IF just supports maximum FHD@60 with: + * - videoclock = 148.5 (MHz) + * - bpp: maximum 24bpp + * - data lanes: maximum 4 lanes + * Therefore maximum hsclk will be 891 Mbps. + */ + + if (hsfreq > 445500) { + clkkpt = 12; + clkbfht = 15; + clkstpt = 48; + golpbkt = 75; + } else if (hsfreq > 250000) { + clkkpt = 7; + clkbfht = 8; + clkstpt = 27; + golpbkt = 40; + } else { + clkkpt = 8; + clkbfht = 6; + clkstpt = 24; + golpbkt = 29; + } + + clstptsetr = CLSTPTSETR_CLKKPT(clkkpt) | CLSTPTSETR_CLKBFHT(clkbfht) | + CLSTPTSETR_CLKSTPT(clkstpt); + rzg2l_mipi_dsi_link_write(dsi->mmio, CLSTPTSETR, clstptsetr); + + lptrnstsetr = LPTRNSTSETR_GOLPBKT(golpbkt); + rzg2l_mipi_dsi_link_write(dsi->mmio, LPTRNSTSETR, lptrnstsetr); + + return 0; +} + +static void rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi *dsi, + const struct drm_display_mode *mode) +{ + u32 vich1ppsetr; + u32 vich1vssetr; + u32 vich1vpsetr; + u32 vich1hssetr; + u32 vich1hpsetr; + int dsi_format; + u32 delay[2]; + u8 index; + + /* Configuration for Pixel Packet */ + dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format); + switch (dsi_format) { + case 24: + vich1ppsetr = VICH1PPSETR_DT_RGB24; + break; + case 18: + vich1ppsetr = VICH1PPSETR_DT_RGB18; + break; + } + + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + vich1ppsetr |= VICH1PPSETR_TXESYNC_PULSE; + + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + vich1ppsetr &= ~VICH1PPSETR_TXESYNC_PULSE; + + rzg2l_mipi_dsi_link_write(dsi->mmio, VICH1PPSETR, vich1ppsetr); + + /* Configuration for Video Parameters */ + vich1vssetr = VICH1VSSETR_VACTIVE(mode->vdisplay) | + VICH1VSSETR_VSA(mode->vsync_end - mode->vsync_start); + vich1vssetr |= (mode->flags & DRM_MODE_FLAG_PVSYNC) ? + VICH1VSSETR_VSPOL_HIGH : VICH1VSSETR_VSPOL_LOW; + + vich1vpsetr = VICH1VPSETR_VFP(mode->vsync_start - mode->vdisplay) | + VICH1VPSETR_VBP(mode->vtotal - mode->vsync_end); + + vich1hssetr = VICH1HSSETR_HACTIVE(mode->hdisplay) | + VICH1HSSETR_HSA(mode->hsync_end - mode->hsync_start); + vich1hssetr |= (mode->flags & DRM_MODE_FLAG_PHSYNC) ? + VICH1HSSETR_HSPOL_HIGH : VICH1HSSETR_HSPOL_LOW; + + vich1hpsetr = VICH1HPSETR_HFP(mode->hsync_start - mode->hdisplay) | + VICH1HPSETR_HBP(mode->htotal - mode->hsync_end); + + rzg2l_mipi_dsi_link_write(dsi->mmio, VICH1VSSETR, vich1vssetr); + rzg2l_mipi_dsi_link_write(dsi->mmio, VICH1VPSETR, vich1vpsetr); + rzg2l_mipi_dsi_link_write(dsi->mmio, VICH1HSSETR, vich1hssetr); + rzg2l_mipi_dsi_link_write(dsi->mmio, VICH1HPSETR, vich1hpsetr); + + /* + * Configuration for Delay Value + * Delay value based on 2 ranges of video clock. + * 74.25MHz is videoclock of HD@60p or FHD@30p + */ + + if (mode->clock > 74250) { + delay[0] = 231; + delay[1] = 216; + } else { + delay[0] = 220; + delay[1] = 212; + } + + if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + index = 0; + else + index = 1; + + rzg2l_mipi_dsi_link_write(dsi->mmio, VICH1SET1R, + VICH1SET1R_DLY(delay[index])); +} + +static int rzg2l_mipi_dsi_start_hs_clock(struct rzg2l_mipi_dsi *dsi) +{ + bool hsclk_running_mode; + u32 hsclksetr; + u32 status; + int ret; + + hsclk_running_mode = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS); + + /* Start HS clock */ + hsclksetr = HSCLKSETR_HSCLKRUN_HS | (hsclk_running_mode ? + HSCLKSETR_HSCLKMODE_CONT : + HSCLKSETR_HSCLKMODE_NON_CONT); + rzg2l_mipi_dsi_link_write(dsi->mmio, HSCLKSETR, hsclksetr); + + if (hsclk_running_mode) { + ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, + status & PLSR_CLLP2HS, + 2000, 20000, false, dsi->mmio, PLSR); + if (ret < 0) { + dev_err(dsi->dev, "failed to start HS clock\n"); + return ret; + } + } + + dev_dbg(dsi->dev, "Start High Speed Clock with %s clock mode", + hsclk_running_mode ? "continuous" : "non-continuous"); + + return 0; +} + +static int rzg2l_mipi_dsi_stop_hs_clock(struct rzg2l_mipi_dsi *dsi) +{ + bool hsclk_mode; + u32 status; + int ret; + + hsclk_mode = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS); + + /* Stop HS clock */ + rzg2l_mipi_dsi_link_write(dsi->mmio, HSCLKSETR, + hsclk_mode ? HSCLKSETR_HSCLKMODE_CONT : + HSCLKSETR_HSCLKMODE_NON_CONT); + + if (hsclk_mode) { + ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, + status & PLSR_CLHS2LP, + 2000, 20000, false, dsi->mmio, PLSR); + if (ret < 0) { + dev_err(dsi->dev, "failed to stop HS clock\n"); + return ret; + } + } + + return 0; +} + +static int rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi *dsi) +{ + u32 vich1set0r; + u32 status; + int ret; + + /* Configuration for Blanking sequence and start video input*/ + vich1set0r = VICH1SET0R_HFPNOLP | VICH1SET0R_HBPNOLP | + VICH1SET0R_HSANOLP | VICH1SET0R_VSTART; + rzg2l_mipi_dsi_link_write(dsi->mmio, VICH1SET0R, vich1set0r); + + ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, + status & VICH1SR_VIRDY, + 2000, 20000, false, dsi->mmio, VICH1SR); + if (ret < 0) { + dev_err(dsi->dev, "Failed to start video signal input\n"); + return ret; + } + + dev_dbg(dsi->dev, "Start video transferring"); + + return 0; +} + +static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi) +{ + u32 status; + int ret; + + rzg2l_mipi_dsi_link_write(dsi->mmio, VICH1SET0R, VICH1SET0R_VSTPAFT); + ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, + (status & VICH1SR_STOP) && (!(status & VICH1SR_RUNNING)), + 2000, 20000, false, dsi->mmio, VICH1SR); + if (ret < 0) + goto err; + + ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, + !(status & LINKSR_HSBUSY), + 2000, 20000, false, dsi->mmio, LINKSR); + if (ret < 0) + goto err; + + return 0; +err: + dev_err(dsi->dev, "Failed to stop video signal input\n"); + return ret; +} + +/* ----------------------------------------------------------------------------- + * Bridge + */ + +static int rzg2l_mipi_dsi_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); + + return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge, + flags); +} + +static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct drm_atomic_state *state = old_bridge_state->base.state; + struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); + const struct drm_display_mode *mode; + struct drm_connector *connector; + struct drm_crtc *crtc; + int ret; + + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); + crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; + mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode; + + ret = rzg2l_mipi_dsi_startup(dsi, mode); + if (ret < 0) + return; + + rzg2l_mipi_dsi_set_display_timing(dsi, mode); + + ret = rzg2l_mipi_dsi_start_hs_clock(dsi); + if (ret < 0) + return; + + ret = rzg2l_mipi_dsi_start_video(dsi); + if (ret < 0) + return; +} + +static void rzg2l_mipi_dsi_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); + + rzg2l_mipi_dsi_stop_video(dsi); + rzg2l_mipi_dsi_stop_hs_clock(dsi); + pm_runtime_put(dsi->dev); + reset_control_assert(dsi->rstc); + reset_control_assert(dsi->arstc); + reset_control_assert(dsi->prstc); +} + +static enum drm_mode_status +rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if (mode->clock > 148500) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static const struct drm_bridge_funcs rzg2l_mipi_dsi_bridge_ops = { + .attach = rzg2l_mipi_dsi_attach, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_enable = rzg2l_mipi_dsi_atomic_enable, + .atomic_disable = rzg2l_mipi_dsi_atomic_disable, + .mode_valid = rzg2l_mipi_dsi_bridge_mode_valid, +}; + +/* ----------------------------------------------------------------------------- + * Host setting + */ + +static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host); + int ret; + + if (device->lanes > dsi->num_data_lanes) + return -EINVAL; + + switch (mipi_dsi_pixel_format_to_bpp(device->format)) { + case 24: + case 18: + break; + default: + dev_warn(dsi->dev, "unsupported format"); + return -EINVAL; + } + + dsi->lanes = device->lanes; + dsi->format = device->format; + dsi->mode_flags = device->mode_flags; + + dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, + 1, 0); + if (IS_ERR(dsi->next_bridge)) { + ret = PTR_ERR(dsi->next_bridge); + dev_err(dsi->dev, "failed to get next bridge: %d\n", ret); + return ret; + } + + /* Initialize the DRM bridge. */ + dsi->bridge.funcs = &rzg2l_mipi_dsi_bridge_ops; + dsi->bridge.of_node = dsi->dev->of_node; + drm_bridge_add(&dsi->bridge); + + return 0; +} + +static int rzg2l_mipi_dsi_host_detach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host); + + drm_bridge_remove(&dsi->bridge); + return 0; +} + +static const struct mipi_dsi_host_ops rzg2l_mipi_dsi_host_ops = { + .attach = rzg2l_mipi_dsi_host_attach, + .detach = rzg2l_mipi_dsi_host_detach, +}; + +/* ----------------------------------------------------------------------------- + * Probe & Remove + */ + +static int rzg2l_mipi_dsi_parse_dt(struct rzg2l_mipi_dsi *dsi) +{ + struct device_node *ep; + u32 data_lanes[4]; + int ret; + + ep = of_graph_get_endpoint_by_regs(dsi->dev->of_node, 1, 0); + if (!ep) { + dev_dbg(dsi->dev, "unconnected port@1\n"); + return -ENODEV; + } + + ret = of_property_read_variable_u32_array(ep, "data-lanes", data_lanes, + 1, 4); + of_node_put(ep); + + if (ret < 0) { + dev_err(dsi->dev, "missing or invalid data-lanes property\n"); + return -ENODEV; + } + + dsi->num_data_lanes = ret; + return 0; +} + +static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) +{ + struct rzg2l_mipi_dsi *dsi; + int ret; + + dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); + if (!dsi) + return -ENOMEM; + + platform_set_drvdata(pdev, dsi); + dsi->dev = &pdev->dev; + + ret = rzg2l_mipi_dsi_parse_dt(dsi); + if (ret < 0) + return ret; + + dsi->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dsi->mmio)) + return PTR_ERR(dsi->mmio); + + dsi->vclk = devm_clk_get(dsi->dev, "vclk"); + if (IS_ERR(dsi->vclk)) + return PTR_ERR(dsi->vclk); + + dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); + if (IS_ERR(dsi->rstc)) + return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), + "failed to get arst\n"); + + dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst"); + if (IS_ERR(dsi->arstc)) + return dev_err_probe(&pdev->dev, PTR_ERR(dsi->arstc), + "failed to get arst\n"); + + dsi->prstc = devm_reset_control_get_exclusive(dsi->dev, "prst"); + if (IS_ERR(dsi->prstc)) + return dev_err_probe(dsi->dev, PTR_ERR(dsi->prstc), + "failed to get prst\n"); + + pm_runtime_enable(dsi->dev); + + /* Init host device */ + dsi->host.dev = dsi->dev; + dsi->host.ops = &rzg2l_mipi_dsi_host_ops; + ret = mipi_dsi_host_register(&dsi->host); + if (ret < 0) + goto out_pm_get; + + return 0; +out_pm_get: + pm_runtime_disable(dsi->dev); + return ret; +} + +static int rzg2l_mipi_dsi_remove(struct platform_device *pdev) +{ + struct rzg2l_mipi_dsi *dsi = platform_get_drvdata(pdev); + + mipi_dsi_host_unregister(&dsi->host); + pm_runtime_disable(&pdev->dev); + return 0; +} + +static const struct of_device_id rzg2l_mipi_dsi_of_table[] = { + { .compatible = "renesas,rzg2l-mipi-dsi" }, + { /* sentinel */ } +}; + +static struct platform_driver rzg2l_mipi_dsi_platform_driver = { + .driver = { + .name = "rzg2l-mipi-dsi", + .of_match_table = rzg2l_mipi_dsi_of_table, + }, + .probe = rzg2l_mipi_dsi_probe, + .remove = rzg2l_mipi_dsi_remove, +}; + +module_platform_driver(rzg2l_mipi_dsi_platform_driver); + +MODULE_AUTHOR("Biju Das <biju.das.jz(a)bp.renesas.com"); +MODULE_DESCRIPTION("Renesas RZ/G2L MIPI DSI Encoder Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h new file mode 100644 index 000000000000..40c96330e79a --- /dev/null +++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RZ/G2L MIPI DSI Interface Registers Definitions + * + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#ifndef __RZG2L_MIPI_DSI_REGS_H__ +#define __RZG2L_MIPI_DSI_REGS_H__ + +/* DPHY Registers */ +#define DSIDPHYCTRL0 0x00 +#define DSIDPHYCTRL0_CAL_EN_HSRX_OFS BIT(16) +#define DSIDPHYCTRL0_CMN_MASTER_EN BIT(8) +#define DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 BIT(2) +#define DSIDPHYCTRL0_EN_LDO1200 BIT(1) +#define DSIDPHYCTRL0_EN_BGR BIT(0) + +#define DSIDPHYTIM0 0x04 +#define DSIDPHYTIM0_TCLK_MISS(x) ((x) << 24) +#define DSIDPHYTIM0_T_INIT(x) ((x) << 0) + +#define DSIDPHYTIM1 0x08 +#define DSIDPHYTIM1_THS_PREPARE(x) ((x) << 24) +#define DSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16) +#define DSIDPHYTIM1_THS_SETTLE(x) ((x) << 8) +#define DSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0) + +#define DSIDPHYTIM2 0x0c +#define DSIDPHYTIM2_TCLK_TRAIL(x) ((x) << 24) +#define DSIDPHYTIM2_TCLK_POST(x) ((x) << 16) +#define DSIDPHYTIM2_TCLK_PRE(x) ((x) << 8) +#define DSIDPHYTIM2_TCLK_ZERO(x) ((x) << 0) + +#define DSIDPHYTIM3 0x10 +#define DSIDPHYTIM3_TLPX(x) ((x) << 24) +#define DSIDPHYTIM3_THS_EXIT(x) ((x) << 16) +#define DSIDPHYTIM3_THS_TRAIL(x) ((x) << 8) +#define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0) + +/* --------------------------------------------------------*/ +/* Link Registers */ +#define LINK_REG_OFFSET 0x10000 + +/* Link Status Register */ +#define LINKSR 0x10 +#define LINKSR_LPBUSY BIT(13) +#define LINKSR_HSBUSY BIT(12) +#define LINKSR_VICHRUN1 BIT(8) +#define LINKSR_SQCHRUN1 BIT(4) +#define LINKSR_SQCHRUN0 BIT(0) + +/* Tx Set Register */ +#define TXSETR 0x100 +#define TXSETR_NUMLANECAP (0x3 << 16) +#define TXSETR_DLEN BIT(9) +#define TXSETR_CLEN BIT(8) +#define TXSETR_NUMLANEUSE(x) (((x) & 0x3) << 0) + +/* HS Clock Set Register */ +#define HSCLKSETR 0x104 +#define HSCLKSETR_HSCLKMODE_CONT BIT(1) +#define HSCLKSETR_HSCLKMODE_NON_CONT (0 << 1) +#define HSCLKSETR_HSCLKRUN_HS BIT(0) +#define HSCLKSETR_HSCLKRUN_LP (0 << 0) + +/* Reset Control Register */ +#define RSTCR 0x110 +#define RSTCR_SWRST BIT(0) +#define RSTCR_FCETXSTP BIT(16) + +/* Reset Status Register */ +#define RSTSR 0x114 +#define RSTSR_DL0DIR BIT(15) +#define RSTSR_DLSTPST (0xf << 8) +#define RSTSR_SWRSTV1 BIT(4) +#define RSTSR_SWRSTIB BIT(3) +#define RSTSR_SWRSTAPB BIT(2) +#define RSTSR_SWRSTLP BIT(1) +#define RSTSR_SWRSTHS BIT(0) + +/* Clock Lane Stop Time Set Register */ +#define CLSTPTSETR 0x314 +#define CLSTPTSETR_CLKKPT(x) ((x) << 24) +#define CLSTPTSETR_CLKBFHT(x) ((x) << 16) +#define CLSTPTSETR_CLKSTPT(x) ((x) << 2) + +/* LP Transition Time Set Register */ +#define LPTRNSTSETR 0x318 +#define LPTRNSTSETR_GOLPBKT(x) ((x) << 0) + +/* Physical Lane Status Register */ +#define PLSR 0x320 +#define PLSR_CLHS2LP BIT(27) +#define PLSR_CLLP2HS BIT(26) + +/* Video-Input Channel 1 Set 0 Register */ +#define VICH1SET0R 0x400 +#define VICH1SET0R_VSEN BIT(12) +#define VICH1SET0R_HFPNOLP BIT(10) +#define VICH1SET0R_HBPNOLP BIT(9) +#define VICH1SET0R_HSANOLP BIT(8) +#define VICH1SET0R_VSTPAFT BIT(1) +#define VICH1SET0R_VSTART BIT(0) + +/* Video-Input Channel 1 Set 1 Register */ +#define VICH1SET1R 0x404 +#define VICH1SET1R_DLY(x) (((x) & 0xfff) << 2) + +/* Video-Input Channel 1 Status Register */ +#define VICH1SR 0x410 +#define VICH1SR_VIRDY BIT(3) +#define VICH1SR_RUNNING BIT(2) +#define VICH1SR_STOP BIT(1) +#define VICH1SR_START BIT(0) + +/* Video-Input Channel 1 Pixel Packet Set Register */ +#define VICH1PPSETR 0x420 +#define VICH1PPSETR_DT_RGB18 (0x1e << 16) +#define VICH1PPSETR_DT_RGB18_LS (0x2e << 16) +#define VICH1PPSETR_DT_RGB24 (0x3e << 16) +#define VICH1PPSETR_TXESYNC_PULSE BIT(15) +#define VICH1PPSETR_VC(x) ((x) << 22) + +/* Video-Input Channel 1 Vertical Size Set Register */ +#define VICH1VSSETR 0x428 +#define VICH1VSSETR_VACTIVE(x) (((x) & 0x7fff) << 16) +#define VICH1VSSETR_VSPOL_LOW BIT(15) +#define VICH1VSSETR_VSPOL_HIGH (0 << 15) +#define VICH1VSSETR_VSA(x) (((x) & 0xfff) << 0) + +/* Video-Input Channel 1 Vertical Porch Set Register */ +#define VICH1VPSETR 0x42C +#define VICH1VPSETR_VFP(x) (((x) & 0x1fff) << 16) +#define VICH1VPSETR_VBP(x) (((x) & 0x1fff) << 0) + +/* Video-Input Channel 1 Horizontal Size Set Register */ +#define VICH1HSSETR 0x430 +#define VICH1HSSETR_HACTIVE(x) (((x) & 0x7fff) << 16) +#define VICH1HSSETR_HSPOL_LOW BIT(15) +#define VICH1HSSETR_HSPOL_HIGH (0 << 15) +#define VICH1HSSETR_HSA(x) (((x) & 0xfff) << 0) + +/* Video-Input Channel 1 Horizontal Porch Set Register */ +#define VICH1HPSETR 0x434 +#define VICH1HPSETR_HFP(x) (((x) & 0x1fff) << 16) +#define VICH1HPSETR_HBP(x) (((x) & 0x1fff) << 0) + +#endif /* __RZG2L_MIPI_DSI_REGS_H__ */ -- 2.17.1

2 2

Allow ttm_buffer_object without resource
by Christian König 18 Apr '22

18 Apr '22

Hi guys, this patch set cleans up the handling of TTM buffer objects quite a bit by allowing to create them without allocating a ttm_resource as well. That's not only cleaner in general, but also a necessary prerequisite for quite a number of related work. Please review and comment, Christian.

3 14

[PATCH 0/8] drm: Introduce display-helper library
by Thomas Zimmermann 18 Apr '22

18 Apr '22

Move DisplayPort, HDMI and various other display helpers from KMS helpers into a new module. Adapt all drivers. This patch is part of an on-going effort to reduce the minimum size of DRM when linked into the kernel binary. The helpers for various display and video-output standards are not required for minimal graphics output and can be moved into a separate module. The DisplayPort code was already part of the DP module, which now forms the base of the display-helper module. Moving other helpers into the new module reduces KMS helpers by ~14 KiB (from 243 KiB to 229 KiB). More importantly, restructuring the code allows for a more fine-grained selection of helpers and dependencies. Built on x64-64, i586, aarch64, and arm. Thomas Zimmermann (8): drm: Put related statements next to each other in Makefile drm: Rename dp/ to display/ drm/display: Introduce a DRM display-helper module drm/display: Split DisplayPort header into core and helper drm/display: Move DSC header and helpers into display-helper module drm/display: Move HDCP helpers into display-helper module drm/display: Move HDMI helpers into display-helper module drm/display: Move SCDC helpers into display-helper library Documentation/gpu/drm-kms-helpers.rst | 43 +- drivers/gpu/drm/Kconfig | 23 + drivers/gpu/drm/Makefile | 29 +- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 +- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 3 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 1 + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 1 + drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 + drivers/gpu/drm/amd/display/Kconfig | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +- .../drm/amd/display/dc/core/dc_link_dpcd.c | 2 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 + .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 2 +- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.h | 2 +- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 4 +- .../gpu/drm/amd/display/dc/dsc/dscc_types.h | 2 +- .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 +- drivers/gpu/drm/amd/display/dc/os_types.h | 2 +- .../gpu/drm/amd/display/include/dpcd_defs.h | 2 +- .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 4 +- drivers/gpu/drm/bridge/Kconfig | 5 + drivers/gpu/drm/bridge/analogix/Kconfig | 2 + .../drm/bridge/analogix/analogix-anx6345.c | 2 +- .../drm/bridge/analogix/analogix-anx78xx.c | 4 +- .../drm/bridge/analogix/analogix-i2c-dptx.c | 2 +- .../drm/bridge/analogix/analogix_dp_core.h | 2 +- drivers/gpu/drm/bridge/analogix/anx7625.c | 6 +- drivers/gpu/drm/bridge/cadence/Kconfig | 1 + .../drm/bridge/cadence/cdns-mhdp8546-core.c | 4 +- .../drm/bridge/cadence/cdns-mhdp8546-core.h | 2 +- .../drm/bridge/cadence/cdns-mhdp8546-hdcp.c | 2 +- drivers/gpu/drm/bridge/ite-it6505.c | 4 +- drivers/gpu/drm/bridge/parade-ps8640.c | 4 +- drivers/gpu/drm/bridge/sii902x.c | 2 +- drivers/gpu/drm/bridge/sil-sii8620.c | 2 +- drivers/gpu/drm/bridge/synopsys/Kconfig | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +- drivers/gpu/drm/bridge/tc358767.c | 2 +- drivers/gpu/drm/bridge/tc358775.c | 2 +- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 +- drivers/gpu/drm/display/Makefile | 13 + .../drm_display_helper_mod.c} | 10 +- .../gpu/drm/{dp => display}/drm_dp_aux_bus.c | 4 +- .../gpu/drm/{dp => display}/drm_dp_aux_dev.c | 4 +- drivers/gpu/drm/{dp => display}/drm_dp_cec.c | 2 +- .../{dp => display}/drm_dp_dual_mode_helper.c | 2 +- .../{dp/drm_dp.c => display/drm_dp_helper.c} | 4 +- .../{dp => display}/drm_dp_helper_internal.h | 0 .../drm/{dp => display}/drm_dp_mst_topology.c | 2 +- .../drm_dp_mst_topology_internal.h | 2 +- .../{drm_dsc.c => display/drm_dsc_helper.c} | 5 +- .../{drm_hdcp.c => display/drm_hdcp_helper.c} | 4 +- drivers/gpu/drm/display/drm_hdmi_helper.c | 463 +++++++++++ .../gpu/drm/{ => display}/drm_scdc_helper.c | 3 +- drivers/gpu/drm/dp/Makefile | 9 - drivers/gpu/drm/drm_connector.c | 34 - drivers/gpu/drm/drm_edid.c | 439 +---------- drivers/gpu/drm/drm_mipi_dsi.c | 6 +- drivers/gpu/drm/exynos/Kconfig | 1 + drivers/gpu/drm/exynos/exynos_hdmi.c | 2 +- drivers/gpu/drm/gma500/cdv_intel_dp.c | 2 +- drivers/gpu/drm/gma500/intel_bios.c | 3 +- drivers/gpu/drm/hdmi/Makefile | 4 + drivers/gpu/drm/i2c/Kconfig | 1 + drivers/gpu/drm/i2c/tda998x_drv.c | 2 +- drivers/gpu/drm/i915/Kconfig | 2 + drivers/gpu/drm/i915/display/icl_dsi.c | 1 + drivers/gpu/drm/i915/display/intel_bios.c | 3 +- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_types.h | 6 +- drivers/gpu/drm/i915/display/intel_dp.c | 5 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 6 +- .../drm/i915/display/intel_dp_link_training.h | 2 +- drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +- .../gpu/drm/i915/display/intel_qp_tables.c | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 2 + drivers/gpu/drm/mediatek/Kconfig | 1 + drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 +- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/dp/dp_audio.c | 2 +- drivers/gpu/drm/msm/dp/dp_aux.h | 2 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 +- drivers/gpu/drm/msm/edp/edp.h | 3 +- drivers/gpu/drm/msm/edp/edp_ctrl.c | 3 +- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 + drivers/gpu/drm/nouveau/Kconfig | 1 + drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +- drivers/gpu/drm/nouveau/nouveau_connector.h | 2 +- drivers/gpu/drm/nouveau/nouveau_dp.c | 2 +- drivers/gpu/drm/nouveau/nouveau_encoder.h | 6 +- drivers/gpu/drm/omapdrm/Kconfig | 2 + drivers/gpu/drm/omapdrm/dss/hdmi4.c | 1 + drivers/gpu/drm/panel/panel-edp.c | 4 +- .../gpu/drm/panel/panel-samsung-atna33xc20.c | 4 +- drivers/gpu/drm/radeon/atombios_dp.c | 2 +- drivers/gpu/drm/radeon/radeon_audio.c | 1 + drivers/gpu/drm/radeon/radeon_connectors.c | 2 +- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- drivers/gpu/drm/radeon/radeon_mode.h | 4 +- drivers/gpu/drm/rockchip/Kconfig | 2 + .../gpu/drm/rockchip/analogix_dp-rockchip.c | 2 +- drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +- drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +- drivers/gpu/drm/rockchip/inno_hdmi.c | 2 +- drivers/gpu/drm/rockchip/rk3066_hdmi.c | 1 + drivers/gpu/drm/rockchip/rockchip_lvds.c | 2 +- drivers/gpu/drm/rockchip/rockchip_rgb.c | 2 +- .../drm/selftests/test-drm_dp_mst_helper.c | 4 +- drivers/gpu/drm/sti/Kconfig | 1 + drivers/gpu/drm/sti/sti_hdmi.c | 2 +- drivers/gpu/drm/sun4i/Kconfig | 1 + drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 2 +- drivers/gpu/drm/tegra/Kconfig | 1 + drivers/gpu/drm/tegra/dp.c | 2 +- drivers/gpu/drm/tegra/dpaux.c | 4 +- drivers/gpu/drm/tegra/hdmi.c | 1 + drivers/gpu/drm/tegra/sor.c | 5 +- drivers/gpu/drm/vc4/Kconfig | 1 + drivers/gpu/drm/vc4/vc4_hdmi.c | 4 +- drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- drivers/misc/mei/hdcp/mei_hdcp.h | 2 +- .../{dp/drm_dp_helper.h => display/drm_dp.h} | 695 +---------------- include/drm/{dp => display}/drm_dp_aux_bus.h | 0 .../{dp => display}/drm_dp_dual_mode_helper.h | 0 include/drm/display/drm_dp_helper.h | 719 ++++++++++++++++++ .../drm/{dp => display}/drm_dp_mst_helper.h | 2 +- include/drm/{ => display}/drm_dsc.h | 8 +- include/drm/display/drm_dsc_helper.h | 20 + include/drm/{ => display}/drm_hdcp.h | 14 +- include/drm/display/drm_hdcp_helper.h | 22 + include/drm/display/drm_hdmi_helper.h | 36 + .../{drm_scdc_helper.h => display/drm_scdc.h} | 52 +- include/drm/display/drm_scdc_helper.h | 79 ++ include/drm/drm_connector.h | 2 - include/drm/drm_edid.h | 31 +- include/drm/i915_mei_hdcp_interface.h | 2 +- 147 files changed, 1631 insertions(+), 1428 deletions(-) create mode 100644 drivers/gpu/drm/display/Makefile rename drivers/gpu/drm/{dp/drm_dp_helper_mod.c => display/drm_display_helper_mod.c} (51%) rename drivers/gpu/drm/{dp => display}/drm_dp_aux_bus.c (99%) rename drivers/gpu/drm/{dp => display}/drm_dp_aux_dev.c (99%) rename drivers/gpu/drm/{dp => display}/drm_dp_cec.c (99%) rename drivers/gpu/drm/{dp => display}/drm_dp_dual_mode_helper.c (99%) rename drivers/gpu/drm/{dp/drm_dp.c => display/drm_dp_helper.c} (99%) rename drivers/gpu/drm/{dp => display}/drm_dp_helper_internal.h (100%) rename drivers/gpu/drm/{dp => display}/drm_dp_mst_topology.c (99%) rename drivers/gpu/drm/{dp => display}/drm_dp_mst_topology_internal.h (94%) rename drivers/gpu/drm/{drm_dsc.c => display/drm_dsc_helper.c} (99%) rename drivers/gpu/drm/{drm_hdcp.c => display/drm_hdcp_helper.c} (99%) create mode 100644 drivers/gpu/drm/display/drm_hdmi_helper.c rename drivers/gpu/drm/{ => display}/drm_scdc_helper.c (99%) delete mode 100644 drivers/gpu/drm/dp/Makefile create mode 100644 drivers/gpu/drm/hdmi/Makefile rename include/drm/{dp/drm_dp_helper.h => display/drm_dp.h} (74%) rename include/drm/{dp => display}/drm_dp_aux_bus.h (100%) rename include/drm/{dp => display}/drm_dp_dual_mode_helper.h (100%) create mode 100644 include/drm/display/drm_dp_helper.h rename include/drm/{dp => display}/drm_dp_mst_helper.h (99%) rename include/drm/{ => display}/drm_dsc.h (97%) create mode 100644 include/drm/display/drm_dsc_helper.h rename include/drm/{ => display}/drm_hdcp.h (95%) create mode 100644 include/drm/display/drm_hdcp_helper.h create mode 100644 include/drm/display/drm_hdmi_helper.h rename include/drm/{drm_scdc_helper.h => display/drm_scdc.h} (65%) create mode 100644 include/drm/display/drm_scdc_helper.h base-commit: fe83949cd4316608ea785fc376b6ed444224adad prerequisite-patch-id: c2b2f08f0eccc9f5df0c0da49fa1d36267deb11d prerequisite-patch-id: c67e5d886a47b7d0266d81100837557fda34cb24 prerequisite-patch-id: 6e1032c6302461624f33194c8b8f37103a3fa6ef -- 2.35.1

5 32

[Bug 212499] New: nouveau locking issue - WARNING: possible circular locking dependency detected
by bugzilla-daemon＠bugzilla.kernel.org 18 Apr '22

18 Apr '22

https://bugzilla.kernel.org/show_bug.cgi?id=212499 Bug ID: 212499 Summary: nouveau locking issue - WARNING: possible circular locking dependency detected Product: Drivers Version: 2.5 Kernel Version: 5.12-rc5 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: erhard_f(a)mailbox.org CC: dri-devel(a)lists.freedesktop.org Regression: No Created attachment 296155 --> https://bugzilla.kernel.org/attachment.cgi?id=296155&action=edit dmesg (kernel 5.12-rc5, A10-9700E) [...] ====================================================== WARNING: possible circular locking dependency detected 5.12.0-rc5-Excavator #4 Not tainted ------------------------------------------------------ X/593 is trying to acquire lock: ffff95f9110ec518 (&cli->mutex){+.+.}-{3:3}, at: nouveau_bo_move+0x167/0x990 [nouveau] but task is already holding lock: ffff95f8e70281a0 (reservation_ww_class_mutex){+.+.}-{3:3}, at: nouveau_bo_pin+0x3b/0x3c0 [nouveau] which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (reservation_ww_class_mutex){+.+.}-{3:3}: __ww_mutex_lock.constprop.0+0x99/0xf20 nouveau_bo_pin+0x3b/0x3c0 [nouveau] nouveau_channel_prep+0x126/0x2f0 [nouveau] nouveau_channel_new+0x5d/0x6b0 [nouveau] nouveau_abi16_ioctl_channel_alloc+0x10d/0x3a0 [nouveau] drm_ioctl_kernel+0xa8/0xf0 [drm] drm_ioctl+0x20a/0x3a0 [drm] nouveau_drm_ioctl+0x50/0xa0 [nouveau] __x64_sys_ioctl+0x81/0xa0 do_syscall_64+0x33/0x40 entry_SYSCALL_64_after_hwframe+0x44/0xae -> #0 (&cli->mutex){+.+.}-{3:3}: __lock_acquire+0x1480/0x2610 lock_acquire+0xc4/0x390 __mutex_lock+0x78/0x870 nouveau_bo_move+0x167/0x990 [nouveau] ttm_bo_handle_move_mem+0x8b/0x170 [ttm] ttm_bo_validate+0x193/0x1f0 [ttm] nouveau_bo_pin+0x177/0x3c0 [nouveau] nv50_wndw_prepare_fb+0x5a/0x4c0 [nouveau] drm_atomic_helper_prepare_planes+0x85/0x110 [drm_kms_helper] nv50_disp_atomic_commit+0xa6/0x1d0 [nouveau] drm_atomic_helper_update_plane+0xe4/0x140 [drm_kms_helper] drm_mode_cursor_universal+0x126/0x230 [drm] drm_mode_cursor_common+0xfc/0x230 [drm] drm_mode_cursor_ioctl+0x46/0x60 [drm] drm_ioctl_kernel+0xa8/0xf0 [drm] drm_ioctl+0x20a/0x3a0 [drm] nouveau_drm_ioctl+0x50/0xa0 [nouveau] __x64_sys_ioctl+0x81/0xa0 do_syscall_64+0x33/0x40 entry_SYSCALL_64_after_hwframe+0x44/0xae other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(reservation_ww_class_mutex); lock(&cli->mutex); lock(reservation_ww_class_mutex); lock(&cli->mutex); *** DEADLOCK *** 3 locks held by X/593: #0: ffffaae9888e7ce0 (crtc_ww_class_acquire){+.+.}-{0:0}, at: drm_mode_cursor_common+0xbb/0x230 [drm] #1: ffff95f9113b0098 (crtc_ww_class_mutex){+.+.}-{3:3}, at: modeset_lock+0x5f/0x1c0 [drm] #2: ffff95f8e70281a0 (reservation_ww_class_mutex){+.+.}-{3:3}, at: nouveau_bo_pin+0x3b/0x3c0 [nouveau] stack backtrace: CPU: 3 PID: 593 Comm: X Not tainted 5.12.0-rc5-Excavator #4 Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./A320M-HDV R3.0, BIOS P3.10 06/26/2019 Call Trace: dump_stack+0x7f/0xad check_noncircular+0x104/0x120 ? nvkm_uvmm_mthd+0x778/0x7b0 [nouveau] __lock_acquire+0x1480/0x2610 lock_acquire+0xc4/0x390 ? nouveau_bo_move+0x167/0x990 [nouveau] ? nvif_object_mthd+0x112/0x130 [nouveau] __mutex_lock+0x78/0x870 ? nouveau_bo_move+0x167/0x990 [nouveau] ? nouveau_bo_move+0x167/0x990 [nouveau] nouveau_bo_move+0x167/0x990 [nouveau] ? unmap_mapping_pages+0x59/0x120 ttm_bo_handle_move_mem+0x8b/0x170 [ttm] ttm_bo_validate+0x193/0x1f0 [ttm] ? nouveau_bo_sync_for_device+0x9b/0xe0 [nouveau] nouveau_bo_pin+0x177/0x3c0 [nouveau] nv50_wndw_prepare_fb+0x5a/0x4c0 [nouveau] ? _raw_spin_unlock_irqrestore+0x42/0x50 drm_atomic_helper_prepare_planes+0x85/0x110 [drm_kms_helper] ? lockdep_init_map_type+0x47/0x220 nv50_disp_atomic_commit+0xa6/0x1d0 [nouveau] drm_atomic_helper_update_plane+0xe4/0x140 [drm_kms_helper] drm_mode_cursor_universal+0x126/0x230 [drm] drm_mode_cursor_common+0xfc/0x230 [drm] ? drm_mode_setplane+0x1a0/0x1a0 [drm] drm_mode_cursor_ioctl+0x46/0x60 [drm] drm_ioctl_kernel+0xa8/0xf0 [drm] drm_ioctl+0x20a/0x3a0 [drm] ? drm_mode_setplane+0x1a0/0x1a0 [drm] ? lockdep_hardirqs_on_prepare+0xd4/0x180 ? _raw_spin_unlock_irqrestore+0x42/0x50 nouveau_drm_ioctl+0x50/0xa0 [nouveau] __x64_sys_ioctl+0x81/0xa0 do_syscall_64+0x33/0x40 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7f0621dbecc7 Code: 3c 1c 48 f7 d8 49 39 c4 72 b9 e8 24 ff ff ff 85 c0 78 be 5b 4c 89 e0 5d 41 5c c3 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 71 41 0c 00 f7 d8 64 89 01 48 RSP: 002b:00007ffd8eb88dc8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 000000000000000c RCX: 00007f0621dbecc7 RDX: 00007ffd8eb88e1c RSI: 00000000c01c64a3 RDI: 000000000000000c RBP: 00000000c01c64a3 R08: 0000000000000040 R09: 0000000000000001 R10: 00007f0622505bc0 R11: 0000000000000246 R12: 000055fbec3f5ec0 R13: 00007ffd8eb88e1c R14: 00000000000003bc R15: 0000000000000218 # lspci -s 04:00.0 -v 04:00.0 VGA compatible controller: NVIDIA Corporation GK208B [GeForce GT 710] (rev a1) (prog-if 00 [VGA controller]) Subsystem: ASUSTeK Computer Inc. GT710-4H-SL-2GD5 Flags: bus master, fast devsel, latency 0, IRQ 51, IOMMU group 0 Memory at fd000000 (32-bit, non-prefetchable) [size=16M] Memory at e8000000 (64-bit, prefetchable) [size=128M] Memory at f0000000 (64-bit, prefetchable) [size=32M] I/O ports at e000 [size=128] Expansion ROM at 000c0000 [disabled] [size=128K] Capabilities: [60] Power Management version 3 Capabilities: [68] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [78] Express Legacy Endpoint, MSI 00 Capabilities: [100] Virtual Channel Capabilities: [128] Power Budgeting <?> Capabilities: [600] Vendor Specific Information: ID=0001 Rev=1 Len=024 <?> Capabilities: [900] Secondary PCI Express Kernel driver in use: nouveau Kernel modules: nouveau -- You may reply to this email to add a comment. You are receiving this mail because: You are on the CC list for the bug. You are watching the assignee of the bug.

2 2

[Bug 212635] New: nouveau 0000:04:00.0: fifo: fault 00 [READ] at 0000000000380000 engine 00 [GR] client 14 [HUB/SCC] reason 02 [PTE] on channel 5 [007fabf000 X[570]]
by bugzilla-daemon＠bugzilla.kernel.org 18 Apr '22

18 Apr '22

https://bugzilla.kernel.org/show_bug.cgi?id=212635 Bug ID: 212635 Summary: nouveau 0000:04:00.0: fifo: fault 00 [READ] at 0000000000380000 engine 00 [GR] client 14 [HUB/SCC] reason 02 [PTE] on channel 5 [007fabf000 X[570]] Product: Drivers Version: 2.5 Kernel Version: 5.11.12 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: erhard_f(a)mailbox.org Regression: No Created attachment 296315 --> https://bugzilla.kernel.org/attachment.cgi?id=296315&action=edit dmesg (kernel 5.11.12) Happened during browsing on Firefox, WebGL conformance tests were running in the background (https://www.khronos.org/registry/webgl/sdk/tests/webgl-conformance-tests.ht…). The screen went blank, but I got to desktop back again and the machine stayed usable. [...] nouveau 0000:04:00.0: fifo: fault 00 [READ] at 0000000000380000 engine 00 [GR] client 14 [HUB/SCC] reason 02 [PTE] on channel 5 [007fabf000 X[570]] nouveau 0000:04:00.0: fifo: channel 5: killed nouveau 0000:04:00.0: fifo: runlist 0: scheduled for recovery nouveau 0000:04:00.0: fifo: engine 0: scheduled for recovery nouveau 0000:04:00.0: X[570]: channel 5 killed! nouveau 0000:04:00.0: fifo: fault 00 [READ] at 0000000000380000 engine 00 [GR] client 14 [HUB/SCC] reason 02 [PTE] on channel 5 [007fabf000 X[570]] nouveau 0000:04:00.0: fifo: channel 5: killed nouveau 0000:04:00.0: fifo: runlist 0: scheduled for recovery nouveau 0000:04:00.0: fifo: engine 0: scheduled for recovery nouveau 0000:04:00.0: X[570]: channel 5 killed! nouveau 0000:04:00.0: fifo: fault 00 [READ] at 0000000000380000 engine 00 [GR] client 14 [HUB/SCC] reason 02 [PTE] on channel 5 [007fabf000 X[570]] nouveau 0000:04:00.0: fifo: channel 5: killed nouveau 0000:04:00.0: fifo: runlist 0: scheduled for recovery nouveau 0000:04:00.0: fifo: engine 0: scheduled for recovery nouveau 0000:04:00.0: X[570]: channel 5 killed! nouveau 0000:04:00.0: fifo: fault 00 [READ] at 0000000000380000 engine 00 [GR] client 14 [HUB/SCC] reason 02 [PTE] on channel 5 [007fabf000 X[570]] nouveau 0000:04:00.0: fifo: channel 5: killed nouveau 0000:04:00.0: fifo: runlist 0: scheduled for recovery nouveau 0000:04:00.0: fifo: engine 0: scheduled for recovery nouveau 0000:04:00.0: X[570]: channel 5 killed! # inxi -b System: Kernel: 5.11.12-gentoo-Excavator x86_64 bits: 64 Desktop: MATE 1.24.0 Distro: Gentoo Base System release 2.7 Machine: Type: Desktop Mobo: ASRock model: A320M-HDV R3.0 serial: M80-BA024200938 UEFI: American Megatrends v: P3.10 date: 06/26/2019 CPU: Info: Quad Core AMD A10-9700E RADEON R7 10 COMPUTE CORES 4C+6G [MCP] speed: 3300 MHz min/max: 800/3000 MHz Graphics: Device-1: NVIDIA GK208B [GeForce GT 710] driver: nouveau v: kernel Display: x11 server: X.Org 1.20.10 driver: modesetting resolution: 1920x1080~60Hz OpenGL: renderer: NV106 v: 4.3 Mesa 20.3.5 Network: Device-1: Realtek RTL8111/8168/8411 PCI Express Gigabit Ethernet driver: r8169 # lspci 00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Root Complex 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) I/O Memory Management Unit 00:02.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Host Bridge 00:02.4 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Root Port 00:02.5 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Root Port 00:03.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Host Bridge 00:03.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Root Port 00:08.0 Encryption controller: Advanced Micro Devices, Inc. [AMD] Carrizo Platform Security Processor 00:09.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Carrizo Audio Dummy Host Bridge 00:09.2 Audio device: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Audio Controller 00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 20) 00:11.0 SATA controller: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] (rev 49) 00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 49) 00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 4a) 00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev 11) 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Function 0 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Function 1 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Function 2 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Function 3 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Function 4 00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 60h-6fh) Processor Function 5 01:00.0 USB controller: Advanced Micro Devices, Inc. [AMD] Device 43bc (rev 02) 01:00.1 SATA controller: Advanced Micro Devices, Inc. [AMD] Device 43b8 (rev 02) 01:00.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Device 43b3 (rev 02) 02:04.0 PCI bridge: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port (rev 02) 02:06.0 PCI bridge: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port (rev 02) 02:07.0 PCI bridge: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port (rev 02) 04:00.0 VGA compatible controller: NVIDIA Corporation GK208B [GeForce GT 710] (rev a1) 04:00.1 Audio device: NVIDIA Corporation GK208 HDMI/DP Audio Controller (rev a1) 05:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15) 06:00.0 Non-Volatile memory controller: Sandisk Corp WD Black 2019/PC SN750 NVMe SSD 07:00.0 USB controller: ASMedia Technology Inc. ASM2142 USB 3.1 Host Controller -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

2 2

[PATCH v8, 00/15] media: mtk-vcodec: support for M8192 decoder
by Yunfei Dong 18 Apr '22

18 Apr '22

This series adds support for mt8192 h264/vp8/vp9 decoder drivers. Firstly, refactor power/clock/interrupt interfaces for mt8192 is lat and core architecture. Secondly, add new functions to get frame buffer size and resolution according to decoder capability from scp side. Then add callback function to get/put capture buffer in order to enable lat and core decoder in parallel, need to adjust GStreamer at the same time. Then add to support MT21C compressed mode and fix v4l2-compliance fail. Next, extract H264 request api driver to let mt8183 and mt8192 use the same code, and adds mt8192 frame based h264 driver for stateless decoder. Lastly, add vp8 and vp9 stateless decoder drivers. Patches 1 refactor power/clock/interrupt interface. Patches 2~4 get frame buffer size and resolution according to decoder capability. Patches 5 set capture queue bytesused. Patches 6 adjust GStreamer. Patch 7~11 add to support MT21C compressed mode and fix v4l2-compliance fail. patch 12 record capture queue format type. Patch 13~14 extract h264 driver and add mt8192 frame based driver for h264 decoder. Patch 15~16 add vp8 and vp9 stateless decoder drivers. Patch 17 prevent kernel crash when rmmod mtk-vcodec-dec.ko --- changes compared with v6: - adjust GStreamer, separate src buffer done with v4l2_ctrl_request_complete for patch 6. - remove v4l2_m2m_set_dst_buffered. - add new patch to set each plane bytesused in buf prepare for patch 5. - using upstream interface to update vp9 prob tables for patch 16. - fix maintainer comments. - test the driver with chrome VD and GStreamer(H264/VP9/VP8/AV1). changes compared with v6: - rebase to the latest media stage and fix conficts - fix memcpy to memcpy_fromio or memcpy_toio - fix h264 crash when test field bitstream changes compared with v5: - fix vp9 comments for patch 15 - fix vp8 comments for patch 14. - fix comments for patch 12. - fix build errors. changes compared with v4: - fix checkpatch.pl fail. - fix kernel-doc fail. - rebase to the latest media codec driver. changes compared with v3: - remove enum mtk_chip for patch 2. - add vp8 stateless decoder drivers for patch 14. - add vp9 stateless decoder drivers for patch 15. changes compared with v2: - add new patch 11 to record capture queue format type. - separate patch 4 according to tzung-bi's suggestion. - re-write commit message for patch 5 according to tzung-bi's suggestion. changes compared with v1: - rewrite commit message for patch 12. - rewrite cover-letter message. --- Yunfei Dong (17): media: mediatek: vcodec: Add vdec enable/disable hardware helpers media: mediatek: vcodec: Using firmware type to separate different firmware architecture media: mediatek: vcodec: get capture queue buffer size from scp media: mediatek: vcodec: Read max resolution from dec_capability media: mediatek: vcodec: set each plane bytesused in buf prepare media: mediatek: vcodec: Refactor get and put capture buffer flow media: mediatek: vcodec: Refactor supported vdec formats and framesizes media: mediatek: vcodec: Getting supported decoder format types media: mediatek: vcodec: Add format to support MT21C media: mediatek: vcodec: disable vp8 4K capability media: mediatek: vcodec: Fix v4l2-compliance fail media: mediatek: vcodec: record capture queue format type media: mediatek: vcodec: Extract H264 common code media: mediatek: vcodec: support stateless H.264 decoding for mt8192 media: mediatek: vcodec: support stateless VP8 decoding media: mediatek: vcodec: support stateless VP9 decoding media: mediatek: vcodec: prevent kernel crash when rmmod mtk-vcodec-dec.ko .../media/platform/mediatek/vcodec/Makefile | 4 + .../platform/mediatek/vcodec/mtk_vcodec_dec.c | 62 +- .../mediatek/vcodec/mtk_vcodec_dec_drv.c | 8 +- .../mediatek/vcodec/mtk_vcodec_dec_pm.c | 166 +- .../mediatek/vcodec/mtk_vcodec_dec_pm.h | 6 +- .../mediatek/vcodec/mtk_vcodec_dec_stateful.c | 19 +- .../vcodec/mtk_vcodec_dec_stateless.c | 257 +- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 41 +- .../mediatek/vcodec/mtk_vcodec_enc_drv.c | 5 - .../platform/mediatek/vcodec/mtk_vcodec_fw.c | 6 + .../platform/mediatek/vcodec/mtk_vcodec_fw.h | 1 + .../vcodec/vdec/vdec_h264_req_common.c | 310 +++ .../vcodec/vdec/vdec_h264_req_common.h | 272 +++ .../mediatek/vcodec/vdec/vdec_h264_req_if.c | 438 +--- .../vcodec/vdec/vdec_h264_req_multi_if.c | 619 +++++ .../mediatek/vcodec/vdec/vdec_vp8_req_if.c | 437 ++++ .../vcodec/vdec/vdec_vp9_req_lat_if.c | 2072 +++++++++++++++++ .../platform/mediatek/vcodec/vdec_drv_if.c | 37 +- .../platform/mediatek/vcodec/vdec_drv_if.h | 3 + .../platform/mediatek/vcodec/vdec_ipi_msg.h | 36 + .../platform/mediatek/vcodec/vdec_msg_queue.c | 2 + .../platform/mediatek/vcodec/vdec_msg_queue.h | 2 + .../platform/mediatek/vcodec/vdec_vpu_if.c | 53 +- .../platform/mediatek/vcodec/vdec_vpu_if.h | 15 + .../platform/mediatek/vcodec/venc_vpu_if.c | 2 +- include/linux/remoteproc/mtk_scp.h | 2 + 26 files changed, 4274 insertions(+), 601 deletions(-) create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.c create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.h create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_req_if.c create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c -- 2.18.0

6 30

[PATCH 1/2] dt-bindings: lcdif: Add compatible for i.MX8MP
by Marek Vasut 17 Apr '22

17 Apr '22

Add compatible string for i.MX8MP LCDIF variant. This is called LCDIFv3 and is completely different from the LCDIFv3 found in i.MX23 in that it has a completely scrambled register layout compared to all previous LCDIF variants. The new LCDIFv3 also supports 36bit address space. However, except for the complete bit reshuffling, this is still LCDIF and it still works like one. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Alexander Stein <alexander.stein(a)ew.tq-group.com> Cc: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Cc: Lucas Stach <l.stach(a)pengutronix.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: Robby Cai <robby.cai(a)nxp.com> Cc: Sam Ravnborg <sam(a)ravnborg.org> Cc: Stefan Agner <stefan(a)agner.ch> Cc: devicetree(a)vger.kernel.org --- Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index 900a56cae80e6..876015a44a1e6 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -20,6 +20,7 @@ properties: - fsl,imx23-lcdif - fsl,imx28-lcdif - fsl,imx6sx-lcdif + - fsl,imx8mp-lcdif - items: - enum: - fsl,imx6sl-lcdif -- 2.35.1

4 8

[PATCH v2 1/7] drm: mxsfb: Simplify LCDIF clock handling
by Marek Vasut 17 Apr '22

17 Apr '22

The current clock handling in the LCDIF driver is a convoluted mess. Implement runtime PM ops which turn the clock ON and OFF and let the pm_runtime_get_sync()/pm_runtime_put_sync() calls in .atomic_enable and .atomic_disable callbacks turn the clock ON and OFF at the right time. This requires slight reordering in mxsfb_crtc_atomic_enable() and mxsfb_crtc_atomic_disable(), since all the register accesses must happen only with clock enabled and clock frequency configuration must happen with clock disabled. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Alexander Stein <alexander.stein(a)ew.tq-group.com> Cc: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Cc: Lucas Stach <l.stach(a)pengutronix.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Robby Cai <robby.cai(a)nxp.com> Cc: Sam Ravnborg <sam(a)ravnborg.org> Cc: Stefan Agner <stefan(a)agner.ch> --- V2: No change --- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 104 +++++++++++++++++------------- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 27 +++----- 2 files changed, 67 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index 9d71c55a31c07..c790aeff0a6f0 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -73,18 +73,6 @@ static const struct mxsfb_devdata mxsfb_devdata[] = { }, }; -void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb) -{ - if (mxsfb->clk_axi) - clk_prepare_enable(mxsfb->clk_axi); -} - -void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb) -{ - if (mxsfb->clk_axi) - clk_disable_unprepare(mxsfb->clk_axi); -} - static struct drm_framebuffer * mxsfb_fb_create(struct drm_device *dev, struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) @@ -173,13 +161,9 @@ static void mxsfb_irq_disable(struct drm_device *drm) { struct mxsfb_drm_private *mxsfb = drm->dev_private; - mxsfb_enable_axi_clk(mxsfb); - /* Disable and clear VBLANK IRQ */ writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); - - mxsfb_disable_axi_clk(mxsfb); } static int mxsfb_irq_install(struct drm_device *dev, int irq) @@ -225,43 +209,41 @@ static int mxsfb_load(struct drm_device *drm, if (IS_ERR(mxsfb->clk)) return PTR_ERR(mxsfb->clk); - mxsfb->clk_axi = devm_clk_get(drm->dev, "axi"); + mxsfb->clk_axi = devm_clk_get_optional(drm->dev, "axi"); if (IS_ERR(mxsfb->clk_axi)) - mxsfb->clk_axi = NULL; + return PTR_ERR(mxsfb->clk_axi); - mxsfb->clk_disp_axi = devm_clk_get(drm->dev, "disp_axi"); + mxsfb->clk_disp_axi = devm_clk_get_optional(drm->dev, "disp_axi"); if (IS_ERR(mxsfb->clk_disp_axi)) - mxsfb->clk_disp_axi = NULL; + return PTR_ERR(mxsfb->clk_disp_axi); + + platform_set_drvdata(pdev, drm); ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); if (ret) return ret; - pm_runtime_enable(drm->dev); - /* Modeset init */ drm_mode_config_init(drm); ret = mxsfb_kms_init(mxsfb); if (ret < 0) { dev_err(drm->dev, "Failed to initialize KMS pipeline\n"); - goto err_vblank; + return ret; } ret = drm_vblank_init(drm, drm->mode_config.num_crtc); if (ret < 0) { dev_err(drm->dev, "Failed to initialise vblank\n"); - goto err_vblank; + return ret; } /* Start with vertical blanking interrupt reporting disabled. */ drm_crtc_vblank_off(&mxsfb->crtc); ret = mxsfb_attach_bridge(mxsfb); - if (ret) { - dev_err_probe(drm->dev, ret, "Cannot connect bridge\n"); - goto err_vblank; - } + if (ret) + return dev_err_probe(drm->dev, ret, "Cannot connect bridge\n"); drm->mode_config.min_width = MXSFB_MIN_XRES; drm->mode_config.min_height = MXSFB_MIN_YRES; @@ -274,44 +256,37 @@ static int mxsfb_load(struct drm_device *drm, ret = platform_get_irq(pdev, 0); if (ret < 0) - goto err_vblank; + return ret; mxsfb->irq = ret; - pm_runtime_get_sync(drm->dev); ret = mxsfb_irq_install(drm, mxsfb->irq); - pm_runtime_put_sync(drm->dev); - if (ret < 0) { dev_err(drm->dev, "Failed to install IRQ handler\n"); - goto err_vblank; + return ret; } drm_kms_helper_poll_init(drm); - platform_set_drvdata(pdev, drm); - drm_helper_hpd_irq_event(drm); - return 0; - -err_vblank: - pm_runtime_disable(drm->dev); + pm_runtime_enable(drm->dev); - return ret; + return 0; } static void mxsfb_unload(struct drm_device *drm) { + pm_runtime_get_sync(drm->dev); + drm_kms_helper_poll_fini(drm); drm_mode_config_cleanup(drm); - pm_runtime_get_sync(drm->dev); mxsfb_irq_uninstall(drm); + pm_runtime_put_sync(drm->dev); + pm_runtime_disable(drm->dev); drm->dev_private = NULL; - - pm_runtime_disable(drm->dev); } DEFINE_DRM_GEM_CMA_FOPS(fops); @@ -388,23 +363,60 @@ static void mxsfb_shutdown(struct platform_device *pdev) drm_atomic_helper_shutdown(drm); } -#ifdef CONFIG_PM_SLEEP +static int mxsfb_rpm_suspend(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct mxsfb_drm_private *mxsfb = drm->dev_private; + + /* These clock supply the DISPLAY CLOCK Domain */ + clk_disable_unprepare(mxsfb->clk); + /* These clock supply the System Bus, AXI, Write Path, LFIFO */ + clk_disable_unprepare(mxsfb->clk_disp_axi); + /* These clock supply the Control Bus, APB, APBH Ctrl Registers */ + clk_disable_unprepare(mxsfb->clk_axi); + + return 0; +} + +static int mxsfb_rpm_resume(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct mxsfb_drm_private *mxsfb = drm->dev_private; + + /* These clock supply the Control Bus, APB, APBH Ctrl Registers */ + clk_prepare_enable(mxsfb->clk_axi); + /* These clock supply the System Bus, AXI, Write Path, LFIFO */ + clk_prepare_enable(mxsfb->clk_disp_axi); + /* These clock supply the DISPLAY CLOCK Domain */ + clk_prepare_enable(mxsfb->clk); + + return 0; +} + static int mxsfb_suspend(struct device *dev) { struct drm_device *drm = dev_get_drvdata(dev); + int ret; - return drm_mode_config_helper_suspend(drm); + ret = drm_mode_config_helper_suspend(drm); + if (ret) + return ret; + + return mxsfb_rpm_suspend(dev); } static int mxsfb_resume(struct device *dev) { struct drm_device *drm = dev_get_drvdata(dev); + mxsfb_rpm_resume(dev); + return drm_mode_config_helper_resume(drm); } -#endif static const struct dev_pm_ops mxsfb_pm_ops = { + .runtime_suspend = mxsfb_rpm_suspend, + .runtime_resume = mxsfb_rpm_resume, SET_SYSTEM_SLEEP_PM_OPS(mxsfb_suspend, mxsfb_resume) }; diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 4cfb6c0016799..657b6afbbf1f9 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -100,10 +100,6 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) { u32 reg; - if (mxsfb->clk_disp_axi) - clk_prepare_enable(mxsfb->clk_disp_axi); - clk_prepare_enable(mxsfb->clk); - /* Increase number of outstanding requests on all supported IPs */ if (mxsfb->devdata->has_ctrl2) { reg = readl(mxsfb->base + LCDC_V4_CTRL2); @@ -168,10 +164,6 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) reg = readl(mxsfb->base + LCDC_VDCTRL4); reg &= ~VDCTRL4_SYNC_SIGNALS_ON; writel(reg, mxsfb->base + LCDC_VDCTRL4); - - clk_disable_unprepare(mxsfb->clk); - if (mxsfb->clk_disp_axi) - clk_disable_unprepare(mxsfb->clk_disp_axi); } /* @@ -250,8 +242,6 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, mxsfb_set_formats(mxsfb, bus_format); - clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); - if (mxsfb->bridge && mxsfb->bridge->timings) bus_flags = mxsfb->bridge->timings->input_bus_flags; @@ -346,16 +336,12 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); + struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; struct drm_bridge_state *bridge_state; struct drm_device *drm = mxsfb->drm; u32 bus_format = 0; dma_addr_t paddr; - pm_runtime_get_sync(drm->dev); - mxsfb_enable_axi_clk(mxsfb); - - drm_crtc_vblank_on(crtc); - /* If there is a bridge attached to the LCDIF, use its bus format */ if (mxsfb->bridge) { bridge_state = @@ -382,6 +368,10 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, if (!bus_format) bus_format = MEDIA_BUS_FMT_RGB888_1X24; + clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); + + pm_runtime_get_sync(drm->dev); + mxsfb_crtc_mode_set_nofb(mxsfb, bus_format); /* Write cur_buf as well to avoid an initial corrupt frame */ @@ -392,6 +382,8 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, } mxsfb_enable_controller(mxsfb); + + drm_crtc_vblank_on(crtc); } static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, @@ -401,6 +393,8 @@ static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_device *drm = mxsfb->drm; struct drm_pending_vblank_event *event; + drm_crtc_vblank_off(crtc); + mxsfb_disable_controller(mxsfb); spin_lock_irq(&drm->event_lock); @@ -411,9 +405,6 @@ static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, } spin_unlock_irq(&drm->event_lock); - drm_crtc_vblank_off(crtc); - - mxsfb_disable_axi_clk(mxsfb); pm_runtime_put_sync(drm->dev); } -- 2.34.1

2 24

[PATCH] drm/mipi-dbi: Fix max_chunk calculation in spi_transfer
by Yunhao Tian 16 Apr '22

16 Apr '22

In __spi_validate, there's a validation that no partial transfers are accepted (xfer->len % w_size must be zero). When max_chunk is not a multiple of bpw (e.g.max_chunk = 65535, bpw = 16), the transfer will be rejected. This patch clamps max_chunk to the word size, preventing the transfer from being rejected. Signed-off-by: Yunhao Tian <t123yh.xyz(a)gmail.com> --- drivers/gpu/drm/drm_mipi_dbi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c index 71b646c4131f..440dc9fec6cc 100644 --- a/drivers/gpu/drm/drm_mipi_dbi.c +++ b/drivers/gpu/drm/drm_mipi_dbi.c @@ -1182,6 +1182,15 @@ int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, struct spi_message m; size_t chunk; int ret; + int w_size; + + if (bpw <= 8) + w_size = 1; + else if (bpw <= 16) + w_size = 2; + else + w_size = 4; + max_chunk -= (max_chunk % w_size); spi_message_init_with_transfers(&m, &tr, 1); -- 2.25.1

2 1

[PATCH v16 00/22] Add MediaTek SoC DRM (vdosys1) support for mt8195
by Nancy.Lin 16 Apr '22

16 Apr '22

The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, OVL_ADAPTOR and MERGE. Add DRM and these modules support by the patches below: Changes in v16: - fix reviewer comment in v 15 - fix mtk_drm_ddp_comp.c alignment - fix vdosys0 mmsys num before adding vdosys1 patch Changes in v15: - fix ethdr uppercase hex number in dts Changes in v14: - remove MTK_MMSYS 64 bit dependency - add ethdr.yaml back and fix dt_schema check fail Resend v13 - add related maintainer in maillist Changes in v13: - fix reviewer comment in v12 - fix rdma dt-binding format - fix dts node naming - fix 32 bit build error - modify 64bit dependency for mtk-mmsys - rebase to vdosys0 series v16. (ref [5]) Changes in v12: - fix reviewer comment in v11 - modify mbox index - refine dma dev for ovl_adaptor sub driver Changes in v11: - remove ethdr vblank spin lock - refine ovl_adaptor print message Changes in v10: - refine ethdr reset control using devm_reset_control_array_get_optional_exclusive - fix ovl_adaptor mtk_ovl_adaptor_clk_enable error handle issue Changes in v9: - rebase on kernel-5.16-rc1 - rebase on vdosys0 series v13. (ref [5]) - fix ovl_adaptor sub driver is brought up unintentionally - fix clang build test fail- duplicate ethdr/mdp_rdma init_module/cleanup_module symbol issue Changes in v8: - separate merge async reset to new patch. - separate drm ovl_adaptor sub driver to new patch. - fix reviewer comment in v7. Changes in v7: - rebase on vdosys0 series v12 (ref[5]) - add dma description in ethdr binding document. - refine vdosys1 bit definition of mmsys routing table. - separate merge modification into 3 pathces. - separate mutex modification into 2 patches. - add plane color coding for mdp_rdma csc. - move mdp_rdma pm control to ovl_adaptor. - fix reviewer comment in v6. Changes in v6: - rebase on kernel-5.15-rc1. - change mbox label to gce0 for dts node of vdosys1. - modify mmsys reset num for mt8195. - rebase on vdosys0 series v10. (ref [5]) - use drm to bring up ovl_adaptor driver. - move drm iommu/mutex check from kms init to drm bind. - modify rdma binding doc location. (Documentation/devicetree/bindings/arm/) - modify for reviewer's comment in v5. Changes in v5: - add mmsys reset controller reference. Changes in v4: - use merge common driver for merge1~4. - refine ovl_adaptor rdma driver. - use ovl_adaptor ddp_comp function instead of ethdr. - modify for reviewer's comment in v3. Changes in v3: - modify for reviewer's comment in v2. - add vdosys1 2 pixels align limit. - add mixer odd offset support. Changes in v2: - Merge PSEUDO_OVL and ETHDR into one DRM component. - Add mmsys config API for vdosys1 hardware setting. - Add mmsys reset control using linux reset framework. Signed-off-by: Nancy.Lin <nancy.lin(a)mediatek.com> This series are based on the following patch: [1] arm64: dts: Add mediatek SoC mt8195 and evaluation board https://patchwork.kernel.org/project/linux-mediatek/patch/20220112114724.19… [2] arm64: dts: mt8195: add IOMMU and smi nodes https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26… [3] arm64: dts: mt8195: add gce node https://patchwork.kernel.org/project/linux-mediatek/patch/20220126090109.32… [4] [v2] arm64: dts: mt8195: add display node for vdosys0 https://patchwork.kernel.org/project/linux-mediatek/patch/20220225021535.26… [5] Add MediaTek SoC DRM (vdosys0) support for mt8195 https://patchwork.kernel.org/project/linux-mediatek/list/?series=620795 [6] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU https://patchwork.kernel.org/project/linux-mediatek/patch/20220217113453.13… Nancy.Lin (22): dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 dt-bindings: reset: mt8195: add vdosys1 reset control bit dt-bindings: mediatek: add ethdr definition for mt8195 soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 soc: mediatek: change the mutex defines and the mutex_mod type soc: mediatek: add mtk-mutex support for mt8195 vdosys1 drm/mediatek: add display MDP RDMA support for MT8195 drm/mediatek: add display merge advance config API for MT8195 drm/mediatek: add display merge start/stop API for cmdq support drm/mediatek: add display merge mute/unmute support for MT8195 drm/mediatek: add display merge async reset control drm/mediatek: add ETHDR support for MT8195 drm/mediatek: add mediatek-drm plane color encoding info drm/mediatek: add ovl_adaptor support for MT8195 drm/mediatek: add dma dev get function drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support drm/mediatek: add drm ovl_adaptor sub driver for MT8195 drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 arm64: dts: mt8195: add display node for vdosys1 .../arm/mediatek/mediatek,mdp-rdma.yaml | 86 ++++ .../display/mediatek/mediatek,ethdr.yaml | 158 +++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 223 +++++++++ drivers/gpu/drm/mediatek/Makefile | 5 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 29 ++ drivers/gpu/drm/mediatek/mtk_disp_merge.c | 89 +++- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 443 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 55 ++- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 111 +++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 329 +++++++++---- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 13 +- drivers/gpu/drm/mediatek/mtk_drm_plane.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_plane.h | 1 + drivers/gpu/drm/mediatek/mtk_ethdr.c | 376 +++++++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 23 + drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 315 +++++++++++++ drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 20 + drivers/soc/mediatek/mt8195-mmsys.h | 199 ++++++++ drivers/soc/mediatek/mtk-mmsys.c | 79 +++- drivers/soc/mediatek/mtk-mmsys.h | 11 + drivers/soc/mediatek/mtk-mutex.c | 318 +++++++------ include/dt-bindings/reset/mt8195-resets.h | 12 + include/linux/soc/mediatek/mtk-mmsys.h | 22 + 25 files changed, 2636 insertions(+), 295 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h -- 2.18.0

3 31

← Newer
1
...
5
6
7
8
9
10
11
...
78
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel March 2022