dri-devel October 2019

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[PATCH 1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)
by Chris Wilson 03 Oct '19

03 Oct '19

3 6

[Bug 111898] Very Cluttery
by bugzilla-daemon＠freedesktop.org 03 Oct '19

03 Oct '19

https://bugs.freedesktop.org/show_bug.cgi?id=111898 Bug ID: 111898 Summary: Very Cluttery Product: DRI Version: XOrg git Hardware: x86-64 (AMD64) OS: Windows (All) Status: NEW Severity: normal Priority: not set Component: General Assignee: dri-devel(a)lists.freedesktop.org Reporter: shkshabnam203(a)gmail.com Created attachment 145626 --> https://bugs.freedesktop.org/attachment.cgi?id=145626&action=edit Very Cluttery -- You are receiving this mail because: You are the assignee for the bug.

1 0

[PATCH v2] drm/fourcc: Add Arm 16x16 block modifier
by Ayan Halder 03 Oct '19

03 Oct '19

Add the DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED modifier to denote the 16x16 block u-interleaved format used in Arm Utgard and Midgard GPUs. Changes from v1:- 1. Reserved the upper four bits (out of the 56 bits assigned to each vendor) to denote the category of Arm specific modifiers. Currently, we have two categories ie AFBC and MISC. Signed-off-by: Raymond Smith <raymond.smith(a)arm.com> Signed-off-by: Ayan kumar halder <ayan.halder(a)arm.com> --- include/uapi/drm/drm_fourcc.h | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3f987a..b1d3de961109 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -648,7 +648,21 @@ extern "C" { * Further information on the use of AFBC modifiers can be found in * Documentation/gpu/afbc.rst */ -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) + +/* + * The top 4 bits (out of the 56 bits alloted for specifying vendor specific + * modifiers) denote the category for modifiers. Currently we have only two + * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen + * different categories. + */ +#define DRM_FORMAT_MOD_ARM_CODE(type, val) \ + fourcc_mod_code(ARM, ((__u64)type << 52) | ((val) & 0x000fffffffffffffULL)) + +#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 +#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 + +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) /* * AFBC superblock size @@ -742,6 +756,17 @@ extern "C" { */ #define AFBC_FORMAT_MOD_BCH (1ULL << 11) +/* + * Arm 16x16 Block U-Interleaved modifier + * + * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image + * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels + * in the block are reordered. + */ +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) + + /* * Allwinner tiled modifier * -- 2.23.0

3 3

[PATCH v2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)
by Chris Wilson 03 Oct '19

03 Oct '19

Make dma_fence_enable_sw_signaling() behave like its dma_fence_add_callback() and dma_fence_default_wait() counterparts and perform the test to enable signaling under the fence->lock, along with the action to do so. This ensure that should an implementation be trying to flush the cb_list (by signaling) on retirement before freeing the fence, it can do so in a race-free manner. See also 0fc89b6802ba ("dma-fence: Simply wrap dma_fence_signal_locked with dma_fence_signal"). v2: Refactor all 3 enable_signaling paths to use a common function. Signed-off-by: Chris Wilson <chris(a)chris-wilson.co.uk> --- drivers/dma-buf/dma-fence.c | 78 +++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 43 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 2c136aee3e79..4a1442a93f04 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -273,6 +273,30 @@ void dma_fence_free(struct dma_fence *fence) } EXPORT_SYMBOL(dma_fence_free); +static bool __dma_fence_enable_signaling(struct dma_fence *fence) +{ + bool was_set; + + lockdep_assert_held(fence->lock); + + was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &fence->flags); + + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + return true; + + if (!was_set && fence->ops->enable_signaling) { + if (!fence->ops->enable_signaling(fence)) { + dma_fence_signal_locked(fence); + return true; + } + + trace_dma_fence_enable_signal(fence); + } + + return false; +} + /** * dma_fence_enable_sw_signaling - enable signaling on fence * @fence: the fence to enable @@ -285,19 +309,12 @@ void dma_fence_enable_sw_signaling(struct dma_fence *fence) { unsigned long flags; - if (!test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &fence->flags) && - !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && - fence->ops->enable_signaling) { - trace_dma_fence_enable_signal(fence); - - spin_lock_irqsave(fence->lock, flags); - - if (!fence->ops->enable_signaling(fence)) - dma_fence_signal_locked(fence); + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + return; - spin_unlock_irqrestore(fence->lock, flags); - } + spin_lock_irqsave(fence->lock, flags); + __dma_fence_enable_signaling(fence); + spin_unlock_irqrestore(fence->lock, flags); } EXPORT_SYMBOL(dma_fence_enable_sw_signaling); @@ -331,7 +348,6 @@ int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb, { unsigned long flags; int ret = 0; - bool was_set; if (WARN_ON(!fence || !func)) return -EINVAL; @@ -343,25 +359,14 @@ int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb, spin_lock_irqsave(fence->lock, flags); - was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &fence->flags); - - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + if (__dma_fence_enable_signaling(fence)) { + INIT_LIST_HEAD(&cb->node); ret = -ENOENT; - else if (!was_set && fence->ops->enable_signaling) { - trace_dma_fence_enable_signal(fence); - - if (!fence->ops->enable_signaling(fence)) { - dma_fence_signal_locked(fence); - ret = -ENOENT; - } - } - - if (!ret) { + } else { cb->func = func; list_add_tail(&cb->node, &fence->cb_list); - } else - INIT_LIST_HEAD(&cb->node); + } + spin_unlock_irqrestore(fence->lock, flags); return ret; @@ -461,7 +466,6 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) struct default_wait_cb cb; unsigned long flags; signed long ret = timeout ? timeout : 1; - bool was_set; if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) return ret; @@ -473,21 +477,9 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) goto out; } - was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &fence->flags); - - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + if (__dma_fence_enable_signaling(fence)) goto out; - if (!was_set && fence->ops->enable_signaling) { - trace_dma_fence_enable_signal(fence); - - if (!fence->ops->enable_signaling(fence)) { - dma_fence_signal_locked(fence); - goto out; - } - } - if (!timeout) { ret = 0; goto out; -- 2.23.0

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[PATCH] dma-fence: Use non-atomic bitops while under the lock
by Tvrtko Ursulin 03 Oct '19

03 Oct '19

From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> We do not have to use atomic bitops when already under the spinlock. Saves on a handful of lock instruction prefixes, on x86 at least. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Cc: dri-devel(a)lists.freedesktop.org Cc: Chris Wilson <chris(a)chris-wilson.co.uk> --- drivers/dma-buf/dma-fence.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 2c136aee3e79..f0b480042e2f 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -133,15 +133,15 @@ int dma_fence_signal_locked(struct dma_fence *fence) lockdep_assert_held(fence->lock); - if (unlikely(test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, - &fence->flags))) + if (unlikely(__test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, + &fence->flags))) return -EINVAL; /* Stash the cb_list before replacing it with the timestamp */ list_replace(&fence->cb_list, &cb_list); fence->timestamp = ktime_get(); - set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags); + __set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags); trace_dma_fence_signaled(fence); list_for_each_entry_safe(cur, tmp, &cb_list, node) { @@ -343,8 +343,8 @@ int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb, spin_lock_irqsave(fence->lock, flags); - was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &fence->flags); + was_set = __test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &fence->flags); if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) ret = -ENOENT; @@ -473,8 +473,8 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) goto out; } - was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &fence->flags); + was_set = __test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &fence->flags); if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) goto out; -- 2.20.1

1 1

[PATCH] drm: sun8i-ui/vi: Fix layer zpos change/atomic modesetting
by megous＠megous.com 03 Oct '19

03 Oct '19

From: Ondrej Jirman <megous(a)megous.com> There are various issues that this re-work of sun8i_[uv]i_layer_enable function fixes: - Make sure that we re-initialize zpos on reset - Minimize register updates by doing them only when state changes - Fix issue where DE pipe might get disabled even if it is no longer used by the layer that's currently calling sun8i_ui_layer_enable - .atomic_disable callback is not really needed because .atomic_update can do the disable too, so drop the duplicate code Signed-off-by: Ondrej Jirman <megous(a)megous.com> --- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 112 ++++++++++++++++--------- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 112 ++++++++++++++++--------- 2 files changed, 142 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index dd2a1c851939..b88e8ac5ad1c 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -24,10 +24,11 @@ #include "sun8i_ui_scaler.h" static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, - int overlay, bool enable, unsigned int zpos, - unsigned int old_zpos) + int overlay, bool was_enabled, bool enable, + unsigned int zpos, unsigned int old_zpos) { u32 val, bld_base, ch_base; + unsigned int old_pipe_ch; bld_base = sun8i_blender_base(mixer); ch_base = sun8i_channel_base(mixer, channel); @@ -35,28 +36,57 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n", enable ? "En" : "Dis", channel, overlay); - if (enable) - val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN; - else - val = 0; + if (!was_enabled != !enable) { + val = enable ? SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN : 0; - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), - SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val); - - if (!enable || zpos != old_zpos) { regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), - SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), - 0); + SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), + SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val); + } - regmap_update_bits(mixer->engine.regs, + /* + * If this layer was enabled and is being disabled or if it is + * enabled and just changing zpos, clear the old route, if it is + * still configured to this layer in HW. + */ + if ((was_enabled && !enable) || (enable && zpos != old_zpos)) { + /* get channel the pipe for old_zpos is routed to from the HW */ + regmap_read(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), - SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), - 0); + &old_pipe_ch); + old_pipe_ch &= SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos); + old_pipe_ch >>= SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(old_zpos); + + /* + * Check that pipe for old_zpos is still routed to our layer, + * and clear/disable it if it is. + */ + + if (old_pipe_ch == channel) { + DRM_DEBUG_DRIVER("chan=%d en=%d->%d zpos=%d->%d\n", + channel, was_enabled, enable, old_zpos, zpos); + + DRM_DEBUG_DRIVER(" disable pipe %d\n", old_zpos); + + regmap_update_bits(mixer->engine.regs, + SUN8I_MIXER_BLEND_ROUTE(bld_base), + SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), + 0); + + regmap_update_bits(mixer->engine.regs, + SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), + SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), + 0); + } } - if (enable) { + /* + * If enabling this layer or changin zpos, set route to this layer. + */ + if ((enable && !was_enabled) || (enable && zpos != old_zpos)) { + DRM_DEBUG_DRIVER("chan=%d en=%d->%d zpos=%d->%d\n", + channel, was_enabled, enable, old_zpos, zpos); + val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); regmap_update_bits(mixer->engine.regs, @@ -69,6 +99,8 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_BLEND_ROUTE(bld_base), SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos), val); + + DRM_DEBUG_DRIVER(" enable pipe %d <- ch %d\n", zpos, channel); } } @@ -261,45 +293,43 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane, true, true); } -static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane, - struct drm_plane_state *old_state) +static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) { struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); + unsigned int zpos = plane->state->normalized_zpos; unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; + bool was_enabled = old_state->crtc && old_state->visible; + bool enable = plane->state->crtc && plane->state->visible; - sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0, - old_zpos); + if (enable) { + sun8i_ui_layer_update_coord(mixer, layer->channel, + layer->overlay, plane, zpos); + sun8i_ui_layer_update_formats(mixer, layer->channel, + layer->overlay, plane); + sun8i_ui_layer_update_buffer(mixer, layer->channel, + layer->overlay, plane); + } + + sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, + was_enabled, enable, zpos, old_zpos); } -static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, - struct drm_plane_state *old_state) +void sun8i_ui_layer_plane_reset(struct drm_plane *plane) { struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); - unsigned int zpos = plane->state->normalized_zpos; - unsigned int old_zpos = old_state->normalized_zpos; - struct sun8i_mixer *mixer = layer->mixer; - if (!plane->state->visible) { - sun8i_ui_layer_enable(mixer, layer->channel, - layer->overlay, false, 0, old_zpos); + drm_atomic_helper_plane_reset(plane); + if (!plane->state) return; - } - sun8i_ui_layer_update_coord(mixer, layer->channel, - layer->overlay, plane, zpos); - sun8i_ui_layer_update_formats(mixer, layer->channel, - layer->overlay, plane); - sun8i_ui_layer_update_buffer(mixer, layer->channel, - layer->overlay, plane); - sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, - true, zpos, old_zpos); + plane->state->zpos = layer->channel; } static struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = { .prepare_fb = drm_gem_fb_prepare_fb, .atomic_check = sun8i_ui_layer_atomic_check, - .atomic_disable = sun8i_ui_layer_atomic_disable, .atomic_update = sun8i_ui_layer_atomic_update, }; @@ -308,7 +338,7 @@ static const struct drm_plane_funcs sun8i_ui_layer_funcs = { .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, .destroy = drm_plane_cleanup, .disable_plane = drm_atomic_helper_disable_plane, - .reset = drm_atomic_helper_plane_reset, + .reset = sun8i_ui_layer_plane_reset, .update_plane = drm_atomic_helper_update_plane, }; diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index bd0e6a52d1d8..675ebcdac00b 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -18,10 +18,11 @@ #include "sun8i_vi_scaler.h" static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, - int overlay, bool enable, unsigned int zpos, - unsigned int old_zpos) + int overlay, bool was_enabled, bool enable, + unsigned int zpos, unsigned int old_zpos) { u32 val, bld_base, ch_base; + unsigned int old_pipe_ch; bld_base = sun8i_blender_base(mixer); ch_base = sun8i_channel_base(mixer, channel); @@ -29,28 +30,57 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n", enable ? "En" : "Dis", channel, overlay); - if (enable) - val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN; - else - val = 0; - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), - SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val); + if (!was_enabled != !enable) { + val = enable ? SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN : 0; - if (!enable || zpos != old_zpos) { regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), - SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), - 0); + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), + SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val); + } - regmap_update_bits(mixer->engine.regs, + /* + * If this layer was enabled and is being disabled or if it is + * enabled and just changing zpos, clear the old route, if it is + * still configured to this layer in HW. + */ + if ((was_enabled && !enable) || (enable && zpos != old_zpos)) { + /* get channel the pipe for old_zpos is routed to from the HW */ + regmap_read(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), - SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), - 0); + &old_pipe_ch); + old_pipe_ch &= SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos); + old_pipe_ch >>= SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(old_zpos); + + /* + * Check that pipe for old_zpos is still routed to our layer, + * and clear/disable it if it is. + */ + + if (old_pipe_ch == channel) { + DRM_DEBUG_DRIVER("chan=%d en=%d->%d zpos=%d->%d\n", + channel, was_enabled, enable, old_zpos, zpos); + + DRM_DEBUG_DRIVER(" disable pipe %d\n", old_zpos); + + regmap_update_bits(mixer->engine.regs, + SUN8I_MIXER_BLEND_ROUTE(bld_base), + SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), + 0); + + regmap_update_bits(mixer->engine.regs, + SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), + SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), + 0); + } } - if (enable) { + /* + * If enabling this layer or changin zpos, set route to this layer. + */ + if ((enable && !was_enabled) || (enable && zpos != old_zpos)) { + DRM_DEBUG_DRIVER("chan=%d en=%d->%d zpos=%d->%d\n", + channel, was_enabled, enable, old_zpos, zpos); + val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); regmap_update_bits(mixer->engine.regs, @@ -63,6 +93,8 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_BLEND_ROUTE(bld_base), SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos), val); + + DRM_DEBUG_DRIVER(" enable pipe %d <- ch %d\n", zpos, channel); } } @@ -345,45 +377,43 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane, true, true); } -static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane, - struct drm_plane_state *old_state) +static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) { struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); + unsigned int zpos = plane->state->normalized_zpos; unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; + bool was_enabled = old_state->crtc && old_state->visible; + bool enable = plane->state->crtc && plane->state->visible; - sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0, - old_zpos); + if (enable) { + sun8i_vi_layer_update_coord(mixer, layer->channel, + layer->overlay, plane, zpos); + sun8i_vi_layer_update_formats(mixer, layer->channel, + layer->overlay, plane); + sun8i_vi_layer_update_buffer(mixer, layer->channel, + layer->overlay, plane); + } + + sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, + was_enabled, enable, zpos, old_zpos); } -static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, - struct drm_plane_state *old_state) +void sun8i_vi_layer_plane_reset(struct drm_plane *plane) { struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); - unsigned int zpos = plane->state->normalized_zpos; - unsigned int old_zpos = old_state->normalized_zpos; - struct sun8i_mixer *mixer = layer->mixer; - if (!plane->state->visible) { - sun8i_vi_layer_enable(mixer, layer->channel, - layer->overlay, false, 0, old_zpos); + drm_atomic_helper_plane_reset(plane); + if (!plane->state) return; - } - sun8i_vi_layer_update_coord(mixer, layer->channel, - layer->overlay, plane, zpos); - sun8i_vi_layer_update_formats(mixer, layer->channel, - layer->overlay, plane); - sun8i_vi_layer_update_buffer(mixer, layer->channel, - layer->overlay, plane); - sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, - true, zpos, old_zpos); + plane->state->zpos = layer->channel; } static struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = { .prepare_fb = drm_gem_fb_prepare_fb, .atomic_check = sun8i_vi_layer_atomic_check, - .atomic_disable = sun8i_vi_layer_atomic_disable, .atomic_update = sun8i_vi_layer_atomic_update, }; @@ -392,7 +422,7 @@ static const struct drm_plane_funcs sun8i_vi_layer_funcs = { .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, .destroy = drm_plane_cleanup, .disable_plane = drm_atomic_helper_disable_plane, - .reset = drm_atomic_helper_plane_reset, + .reset = sun8i_vi_layer_plane_reset, .update_plane = drm_atomic_helper_update_plane, }; -- 2.23.0

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Outreachy applicant - "dri-devel aka kernel GPU subsystem" Project
by evan chime 03 Oct '19

03 Oct '19

Hello everyone Am Evan Chime, an Outreachy applicant for the December to march Outreachy internship round. Am excited to be here and will like to let you guys know that any help I receive will be highly appreciated. Looking forward to working with you guys Kind regards Evan Get Outlook for iOS<https://aka.ms/o0ukef>

1 1

[Bug 109955] amdgpu [RX Vega 64] system freeze while gaming
by bugzilla-daemon＠freedesktop.org 03 Oct '19

03 Oct '19

https://bugs.freedesktop.org/show_bug.cgi?id=109955 --- Comment #111 from Yury Zhuravlev <stalkerg(a)gmail.com> --- Ok, it's many times was here: echo 7 > /sys/class/drm/card0/device/pp_dpm_sclk this thing also helped me. Without it, many games make my PC is freeze even without anything in logs or working ssh. Something wrong with the PowerPlay system on Vega cards. Can anybody open a ticket on the kernel bug tracker? -- You are receiving this mail because: You are the assignee for the bug.

1 0

[RFC PATCH] pci: prevent putting pcie devices into lower device states on certain intel bridges
by Karol Herbst 03 Oct '19

03 Oct '19

Fixes runpm breakage mainly on Nvidia GPUs as they are not able to resume. Works perfectly with this workaround applied. RFC comment: We are quite sure that there is a higher amount of bridges affected by this, but I was only testing it on my own machine for now. I've stresstested runpm by doing 5000 runpm cycles with that patch applied and never saw it fail. I mainly wanted to get a discussion going on if that's a feasable workaround indeed or if we need something better. I am also sure, that the nouveau driver itself isn't at fault as I am able to reproduce the same issue by poking into some PCI registers on the PCIe bridge to put the GPU into D3cold as it's done in ACPI code. I've written a little python script to reproduce this issue without the need of loading nouveau: https://raw.githubusercontent.com/karolherbst/pci-stub-runpm/master/nv_runp… Signed-off-by: Karol Herbst <kherbst(a)redhat.com> Cc: Bjorn Helgaas <bhelgaas(a)google.com> Cc: Lyude Paul <lyude(a)redhat.com> Cc: linux-pci(a)vger.kernel.org Cc: dri-devel(a)lists.freedesktop.org Cc: nouveau(a)lists.freedesktop.org --- drivers/pci/pci.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 088fcdc8d2b4..9dbd29ced1ac 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -799,6 +799,42 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev) return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false; } +/* + * some intel bridges cause serious issues with runpm if the client device + * is put into D1/D2/D3hot before putting the client into D3cold via + * platform means (generally ACPI). + * + * skipping this makes runpm work perfectly fine on such devices. + * + * As far as we know only skylake and kaby lake SoCs are affected. + */ +static unsigned short intel_broken_d3_bridges[] = { + /* kbl */ + 0x1901, +}; + +static inline bool intel_broken_pci_pm(struct pci_bus *bus) +{ + struct pci_dev *bridge; + int i; + + if (!bus || !bus->self) + return false; + + bridge = bus->self; + if (bridge->vendor != PCI_VENDOR_ID_INTEL) + return false; + + for (i = 0; i < ARRAY_SIZE(intel_broken_d3_bridges); i++) { + if (bridge->device == intel_broken_d3_bridges[i]) { + pci_err(bridge, "found broken intel bridge\n"); + return true; + } + } + + return false; +} + /** * pci_raw_set_power_state - Use PCI PM registers to set the power state of * given PCI device @@ -827,6 +863,9 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) if (state < PCI_D0 || state > PCI_D3hot) return -EINVAL; + if (state != PCI_D0 && intel_broken_pci_pm(dev->bus)) + return 0; + /* * Validate current state: * Can enter D0 from any state, but if we can only go deeper -- 2.21.0

5 17

[PATCH v9 0/5] DMA-BUF Heaps (destaging ION)
by John Stultz 03 Oct '19

03 Oct '19

Here is yet another pass at the dma-buf heaps patchset Andrew and I have been working on which tries to destage a fair chunk of ION functionality. The patchset implements per-heap devices which can be opened directly and then an ioctl is used to allocate a dmabuf from the heap. The interface is similar, but much simpler then IONs, only providing an ALLOC ioctl. Also, I've provided relatively simple system and cma heaps. I've booted and tested these patches with AOSP on the HiKey960 using the kernel tree here: https://git.linaro.org/people/john.stultz/android-dev.git/log/?h=dev/dma-bu… And the userspace changes here: https://android-review.googlesource.com/c/device/linaro/hikey/+/909436 Compared to ION, this patchset is missing the system-contig, carveout and chunk heaps, as I don't have a device that uses those, so I'm unable to do much useful validation there. Additionally we have no upstream users of chunk or carveout, and the system-contig has been deprecated in the common/andoid-* kernels, so this should be ok. I've also removed the stats accounting, since any such accounting should be implemented by dma-buf core or the heaps themselves. New in v9: * Removing needless check in cma heap (noted by Brian Starkey) * Rename dma_heap_get_data->dma_heap_get_drvdata (suggested by Hilf Danton) * Check signals after clearing memory pages to avoid doing needless work if the task is killed (suggested by Hilf) * Better test error reporting (suggested d by Brian) * Other minor cleanups (suggested by Brian) Thoughts and feedback would be greatly appreciated! thanks -john Cc: Laura Abbott <labbott(a)redhat.com> Cc: Benjamin Gaignard <benjamin.gaignard(a)linaro.org> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: Liam Mark <lmark(a)codeaurora.org> Cc: Pratik Patel <pratikp(a)codeaurora.org> Cc: Brian Starkey <Brian.Starkey(a)arm.com> Cc: Vincent Donnefort <Vincent.Donnefort(a)arm.com> Cc: Sudipto Paul <Sudipto.Paul(a)arm.com> Cc: Andrew F. Davis <afd(a)ti.com> Cc: Christoph Hellwig <hch(a)infradead.org> Cc: Chenbo Feng <fengc(a)google.com> Cc: Alistair Strachan <astrachan(a)google.com> Cc: Hridya Valsaraju <hridya(a)google.com> Cc: Hillf Danton <hdanton(a)sina.com> Cc: dri-devel(a)lists.freedesktop.org Andrew F. Davis (1): dma-buf: Add dma-buf heaps framework John Stultz (4): dma-buf: heaps: Add heap helpers dma-buf: heaps: Add system heap to dmabuf heaps dma-buf: heaps: Add CMA heap to dmabuf heaps kselftests: Add dma-heap test MAINTAINERS | 18 ++ drivers/dma-buf/Kconfig | 11 + drivers/dma-buf/Makefile | 2 + drivers/dma-buf/dma-heap.c | 250 ++++++++++++++++ drivers/dma-buf/heaps/Kconfig | 14 + drivers/dma-buf/heaps/Makefile | 4 + drivers/dma-buf/heaps/cma_heap.c | 169 +++++++++++ drivers/dma-buf/heaps/heap-helpers.c | 266 ++++++++++++++++++ drivers/dma-buf/heaps/heap-helpers.h | 55 ++++ drivers/dma-buf/heaps/system_heap.c | 122 ++++++++ include/linux/dma-heap.h | 59 ++++ include/uapi/linux/dma-heap.h | 55 ++++ tools/testing/selftests/dmabuf-heaps/Makefile | 9 + .../selftests/dmabuf-heaps/dmabuf-heap.c | 238 ++++++++++++++++ 14 files changed, 1272 insertions(+) create mode 100644 drivers/dma-buf/dma-heap.c create mode 100644 drivers/dma-buf/heaps/Kconfig create mode 100644 drivers/dma-buf/heaps/Makefile create mode 100644 drivers/dma-buf/heaps/cma_heap.c create mode 100644 drivers/dma-buf/heaps/heap-helpers.c create mode 100644 drivers/dma-buf/heaps/heap-helpers.h create mode 100644 drivers/dma-buf/heaps/system_heap.c create mode 100644 include/linux/dma-heap.h create mode 100644 include/uapi/linux/dma-heap.h create mode 100644 tools/testing/selftests/dmabuf-heaps/Makefile create mode 100644 tools/testing/selftests/dmabuf-heaps/dmabuf-heap.c -- 2.17.1

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dri-devel October 2019