dri-devel March 2022

dri-devel@lists.freedesktop.org

370 participants
780 discussions

[PATCH] drm/amdgpu: Add support for drm_privacy_screen
by Sean Paul 08 Mar '22

08 Mar '22

From: Sean Paul <seanpaul(a)chromium.org> This patch adds the necessary hooks to make amdgpu aware of privacy screens. On devices with privacy screen drivers (such as thinkpad-acpi), the amdgpu driver will defer probe until it's ready and then sync the sw and hw state on each commit the connector is involved and enabled. Signed-off-by: Sean Paul <seanpaul(a)chromium.org> --- I tested this locally, but am not super confident everything is in the correct place. Hopefully the intent of the patch is clear and we can tweak positioning if needed. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 16 +++++++++++++++- 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 2ab675123ae3..e2cfae56c020 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -26,6 +26,7 @@ #include <drm/drm_aperture.h> #include <drm/drm_drv.h> #include <drm/drm_gem.h> +#include <drm/drm_privacy_screen_consumer.h> #include <drm/drm_vblank.h> #include <drm/drm_managed.h> #include "amdgpu_drv.h" @@ -1988,6 +1989,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, { struct drm_device *ddev; struct amdgpu_device *adev; + struct drm_privacy_screen *privacy_screen; unsigned long flags = ent->driver_data; int ret, retry = 0, i; bool supports_atomic = false; @@ -2063,6 +2065,13 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, size = pci_resource_len(pdev, 0); is_fw_fb = amdgpu_is_fw_framebuffer(base, size); + /* If the LCD panel has a privacy screen, defer probe until its ready */ + privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); + if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + drm_privacy_screen_put(privacy_screen); + /* Get rid of things like offb */ ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); if (ret) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e1d3db3fe8de..9e2bb6523add 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9781,6 +9781,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) if (acrtc) { new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); + + /* Sync the privacy screen state between hw and sw */ + drm_connector_update_privacy_screen(new_con_state); } /* Skip any modesets/resets */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 740435ae3997..e369fc95585e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -27,6 +27,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/dp/drm_dp_mst_helper.h> #include <drm/dp/drm_dp_helper.h> +#include <drm/drm_privacy_screen_consumer.h> #include "dm_services.h" #include "amdgpu.h" #include "amdgpu_dm.h" @@ -506,6 +507,7 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector, int link_index) { + struct drm_device *dev = dm->ddev; struct dc_link_settings max_link_enc_cap = {0}; aconnector->dm_dp_aux.aux.name = @@ -519,8 +521,20 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, &aconnector->base); - if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) + if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { + struct drm_privacy_screen *privacy_screen; + + /* Reference given up in drm_connector_cleanup() */ + privacy_screen = drm_privacy_screen_get(dev->dev, NULL); + if (!IS_ERR(privacy_screen)) { + drm_connector_attach_privacy_screen_provider(&aconnector->base, + privacy_screen); + } else { + drm_err(dev, "Error getting privacy screen, ret=%d\n", + PTR_ERR(privacy_screen)); + } return; + } dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); aconnector->mst_mgr.cbs = &dm_mst_cbs; -- Sean Paul, Software Engineer, Google / Chromium OS

3 3

[PATCH] drm/msm/gpu: Fix crash on devices without devfreq support (v2)
by Rob Clark 08 Mar '22

08 Mar '22

From: Rob Clark <robdclark(a)chromium.org> Avoid going down devfreq paths on devices where devfreq is not initialized. v2: Change has_devfreq() logic [Dmitry] Reported-by: Linux Kernel Functional Testing <lkft(a)linaro.org> Reported-by: Anders Roxell <anders.roxell(a)linaro.org> Signed-off-by: Rob Clark <robdclark(a)chromium.org> --- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 30 ++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index 9bf319be11f6..12641616acd3 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -83,6 +83,12 @@ static struct devfreq_dev_profile msm_devfreq_profile = { static void msm_devfreq_boost_work(struct kthread_work *work); static void msm_devfreq_idle_work(struct kthread_work *work); +static bool has_devfreq(struct msm_gpu *gpu) +{ + struct msm_gpu_devfreq *df = &gpu->devfreq; + return !!df->devfreq; +} + void msm_devfreq_init(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; @@ -149,6 +155,9 @@ void msm_devfreq_cleanup(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; + if (!has_devfreq(gpu)) + return; + devfreq_cooling_unregister(gpu->cooling); dev_pm_qos_remove_request(&df->boost_freq); dev_pm_qos_remove_request(&df->idle_freq); @@ -156,16 +165,24 @@ void msm_devfreq_cleanup(struct msm_gpu *gpu) void msm_devfreq_resume(struct msm_gpu *gpu) { - gpu->devfreq.busy_cycles = 0; - gpu->devfreq.time = ktime_get(); + struct msm_gpu_devfreq *df = &gpu->devfreq; - devfreq_resume_device(gpu->devfreq.devfreq); + if (!has_devfreq(gpu)) + return; + + df->busy_cycles = 0; + df->time = ktime_get(); + + devfreq_resume_device(df->devfreq); } void msm_devfreq_suspend(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; + if (!has_devfreq(gpu)) + return; + devfreq_suspend_device(df->devfreq); cancel_idle_work(df); @@ -185,6 +202,9 @@ void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor) struct msm_gpu_devfreq *df = &gpu->devfreq; uint64_t freq; + if (!has_devfreq(gpu)) + return; + freq = get_freq(gpu); freq *= factor; @@ -207,7 +227,7 @@ void msm_devfreq_active(struct msm_gpu *gpu) struct devfreq_dev_status status; unsigned int idle_time; - if (!df->devfreq) + if (!has_devfreq(gpu)) return; /* @@ -253,7 +273,7 @@ void msm_devfreq_idle(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; - if (!df->devfreq) + if (!has_devfreq(gpu)) return; msm_hrtimer_queue_work(&df->idle_work, ms_to_ktime(1), -- 2.35.1

3 3

[PATCH] drm/msm/adreno: fix cast in adreno_get_param()
by Dan Carpenter 08 Mar '22

08 Mar '22

These casts need to happen before the shift. The only time it would matter would be if "rev.core" is >= 128. In that case the sign bit would be extended and we do not want that. Fixes: afab9d91d872 ("drm/msm/adreno: Expose speedbin to userspace") Signed-off-by: Dan Carpenter <dan.carpenter(a)oracle.com> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 15c8997b7251..f7b3f6d266a9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -244,10 +244,10 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; return 0; case MSM_PARAM_CHIP_ID: - *value = (uint64_t) adreno_gpu->rev.patchid | - (uint64_t) (adreno_gpu->rev.minor << 8) | - (uint64_t) (adreno_gpu->rev.major << 16) | - (uint64_t) (adreno_gpu->rev.core << 24); + *value = (uint64_t)adreno_gpu->rev.patchid | + ((uint64_t)adreno_gpu->rev.minor << 8) | + ((uint64_t)adreno_gpu->rev.major << 16) | + ((uint64_t)adreno_gpu->rev.core << 24); if (!adreno_gpu->info->revn) *value |= ((uint64_t) adreno_gpu->speedbin) << 32; return 0; -- 2.20.1

3 2

[PATCH 0/6] drm writeback connector changes
by Kandpal Suraj 08 Mar '22

08 Mar '22

This patch series contains drm_writeback_connector structure change i.e change of drm_connector and drm_encoder fields to a pointer the reason for which is explained in patch(1/6) drm: add writeback pointers to drm_connector and the accompanying changes to the different drivers that were effected by it. I had perviously floated a patch series but missed some of the drivers that were effected by the change hence refloating the patch series Kandpal Suraj (6): drm: add writeback pointers to drm_connector drm/arm/komeda : change driver to use drm_writeback_connector.base pointer drm/vkms: change vkms driver to use drm_writeback_connector.base pointer drm/vc4: vc4 driver changes to accommodate changes done in drm_writeback_connector structure drm/rcar_du: changes to rcar-du driver resulting from drm_writeback_connector structure changes drm/arm: changes to malidp driver resulting from drm_writeback_connector structure changes .../gpu/drm/arm/display/komeda/komeda_crtc.c | 2 +- .../gpu/drm/arm/display/komeda/komeda_kms.h | 3 ++- .../arm/display/komeda/komeda_wb_connector.c | 11 +++++----- drivers/gpu/drm/arm/malidp_crtc.c | 2 +- drivers/gpu/drm/arm/malidp_drv.h | 2 ++ drivers/gpu/drm/arm/malidp_mw.c | 12 +++++++---- drivers/gpu/drm/drm_writeback.c | 19 +++++++++--------- drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 2 ++ drivers/gpu/drm/rcar-du/rcar_du_writeback.c | 8 +++++--- drivers/gpu/drm/vc4/vc4_txp.c | 20 +++++++++++++------ drivers/gpu/drm/vkms/vkms_writeback.c | 9 ++++++--- include/drm/drm_connector.h | 3 +++ include/drm/drm_writeback.h | 6 +++--- 13 files changed, 63 insertions(+), 36 deletions(-) -- 2.17.1

9 46

[PATCH 00/10] drm/gma500: Various cleanups to GEM code
by Thomas Zimmermann 08 Mar '22

08 Mar '22

Refactor and simplify various parts of the memory management. This includes locking, initialization and finalizer functions, and code organization. Tested on Atom N2800 hardware. Thomas Zimmermann (10): drm/gma500: Remove struct psb_gem_object.npage drm/gma500: Acquire reservation lock for GEM objects drm/gma500: Move GTT locking into GTT helpers drm/gma500: Remove struct psb_gtt.sem sempahore drm/gma500: Move GTT setup and restoration into helper funtions drm/gma500: Move GTT resume logic out of psb_gtt_init() drm/gma500: Cleanup GTT uninit and error handling drm/gma500: Split GTT init/resume/fini into GTT and GEM functions drm/gma500: Inline psb_gtt_restore() drm/gma500: Move GEM memory management functions to gem.c drivers/gpu/drm/gma500/gem.c | 161 ++++++++++++++++-- drivers/gpu/drm/gma500/gem.h | 13 +- drivers/gpu/drm/gma500/gma_display.c | 8 +- drivers/gpu/drm/gma500/gtt.c | 239 +++++++++++++-------------- drivers/gpu/drm/gma500/gtt.h | 8 +- drivers/gpu/drm/gma500/power.c | 5 +- drivers/gpu/drm/gma500/psb_drv.c | 13 +- drivers/gpu/drm/gma500/psb_drv.h | 1 - 8 files changed, 296 insertions(+), 152 deletions(-) base-commit: 710a019ad85e96e66f7d75ee7f4733cdd8a2b0d0 prerequisite-patch-id: c2b2f08f0eccc9f5df0c0da49fa1d36267deb11d prerequisite-patch-id: c67e5d886a47b7d0266d81100837557fda34cb24 prerequisite-patch-id: 6e1032c6302461624f33194c8b8f37103a3fa6ef -- 2.35.1

3 16

[PATCH] drm/i915/xehp: Drop aux table invalidation on FlatCCS platforms
by Matt Roper 08 Mar '22

08 Mar '22

Platforms with FlatCCS do not use auxiliary planes for compression control data and thus do not need traditional aux table invalidation (and the registers no longer even exist). Original-author: CQ Tang Signed-off-by: Matt Roper <matthew.d.roper(a)intel.com> --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 28 ++++++++++++++++-------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 1f8cf4f790b2..13bbbf5d9737 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -231,7 +231,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) if (mode & EMIT_INVALIDATE) { u32 flags = 0; - u32 *cs; + u32 *cs, count; flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE; flags |= PIPE_CONTROL_TLB_INVALIDATE; @@ -246,7 +246,12 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) flags |= PIPE_CONTROL_CS_STALL; - cs = intel_ring_begin(rq, 8 + 4); + if (!HAS_FLAT_CCS(rq->engine->i915)) + count = 8 + 4; + else + count = 8; + + cs = intel_ring_begin(rq, count); if (IS_ERR(cs)) return PTR_ERR(cs); @@ -259,8 +264,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); - /* hsdes: 1809175790 */ - cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs); + if (!HAS_FLAT_CCS(rq->engine->i915)) { + /* hsdes: 1809175790 */ + cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs); + } *cs++ = preparser_disable(false); intel_ring_advance(rq, cs); @@ -275,12 +282,15 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) u32 cmd, *cs; cmd = 4; - if (mode & EMIT_INVALIDATE) + if (mode & EMIT_INVALIDATE) { cmd += 2; - if (mode & EMIT_INVALIDATE) - aux_inv = rq->engine->mask & ~BIT(BCS0); - if (aux_inv) - cmd += 2 * hweight32(aux_inv) + 2; + + if (!HAS_FLAT_CCS(rq->engine->i915)) { + aux_inv = rq->engine->mask & ~BIT(BCS0); + if (aux_inv) + cmd += 2 * hweight32(aux_inv) + 2; + } + } cs = intel_ring_begin(rq, cmd); if (IS_ERR(cs)) -- 2.34.1

2 1

Mandatory Test Suite for KMS Drivers?
by Maxime Ripard 08 Mar '22

08 Mar '22

Hi, Back at XDC we floated the idea of creating a test suite for IGT that we expect any KMS driver to pass, similar to what v4l2-compliance and cec-compliance provide for v4l2 and CEC respectively. I was looking at the list of tests, and it's fairly massive, so it's not clear to me what tests we could start this suite with. I can only assume all the KMS (but the chamelium ones) and fbdev related ones would be a good start? What do you think? Maxime

3 4

[PATCH 1/2] drm/amdkfd: CRIU remove sync and TLB flush on restore
by David Yat Sin 08 Mar '22

08 Mar '22

When the process is getting restored, the queues are not mapped yet, so there is no VMID assigned for this process and no TLBs to flush. Signed-off-by: David Yat Sin <david.yatsin(a)amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling(a)amd.com> --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 30 +----------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 59d3fe269e7c..789bdfbd3f9b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2102,7 +2102,6 @@ static int criu_restore_bos(struct kfd_process *p, struct kfd_criu_bo_bucket *bo_buckets = NULL; struct kfd_criu_bo_priv_data *bo_privs = NULL; const bool criu_resume = true; - bool flush_tlbs = false; int ret = 0, j = 0; uint32_t i = 0; @@ -2248,7 +2247,6 @@ static int criu_restore_bos(struct kfd_process *p, for (j = 0; j < p->n_pdds; j++) { struct kfd_dev *peer; struct kfd_process_device *peer_pdd; - bool table_freed = false; if (!bo_priv->mapped_gpuids[j]) break; @@ -2268,20 +2266,11 @@ static int criu_restore_bos(struct kfd_process *p, pr_debug("map mem in restore ioctl -> 0x%llx\n", ((struct kgd_mem *)mem)->va); ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, - (struct kgd_mem *)mem, peer_pdd->drm_priv, &table_freed); + (struct kgd_mem *)mem, peer_pdd->drm_priv, NULL); if (ret) { pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds); goto exit; } - if (table_freed) - flush_tlbs = true; - } - - ret = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, - (struct kgd_mem *) mem, true); - if (ret) { - pr_debug("Sync memory failed, wait interrupted by user signal\n"); - goto exit; } pr_debug("map memory was successful for the BO\n"); @@ -2296,23 +2285,6 @@ static int criu_restore_bos(struct kfd_process *p, } } /* done */ - if (flush_tlbs) { - /* Flush TLBs after waiting for the page table updates to complete */ - for (j = 0; j < p->n_pdds; j++) { - struct kfd_dev *peer; - struct kfd_process_device *pdd = p->pdds[j]; - struct kfd_process_device *peer_pdd; - - peer = kfd_device_by_id(pdd->dev->id); - if (WARN_ON_ONCE(!peer)) - continue; - peer_pdd = kfd_get_process_device_data(peer, p); - if (WARN_ON_ONCE(!peer_pdd)) - continue; - kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); - } - } - /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */ ret = copy_to_user((void __user *)args->bos, bo_buckets, -- 2.17.1

2 2

[PATCH v2 0/2] Revert vendor property from anx7625 bindings
by Robert Foss 08 Mar '22

08 Mar '22

An issue[1] related to how the V4L2_FWNODE_BUS_TYPE_PARALLEL flag is mis-used was found in recent addition to the anx7625 driver. As used currently CPI (camera parallel interface) and DPI (display parallel interface) would share the V4L2_FWNODE_BUS_TYPE_PARALLEL enum. I think that would be perfectly functional, but it is not what V4L2_FWNODE_BUS_TYPE_PARALLEL is documented to represent. As far as I can see it's only intended to represent CPI. Instead of having V4L2_FWNODE_BUS_TYPE_PARALLEL represent two standards, I think they should be split. And possibly V4L2_FWNODE_BUS_TYPE_PARALLEL should be renamed for CPI, but that is a separate story. This would provide for the neatest and most legible solution. If this solution is implemented, this range would be incorrect. Additionally the snippet reverted in 2/2 of this series would no longer be valid. As it stands V4L2_FWNODE_BUS_TYPE_PARALLEL was used to represent DPI due to not being caught in the review process. In order to not introduce this issue into the ABI, let's revert the changes to the anx7625 dt-binding related to this. [1] https://lore.kernel.org/all/YiTruiCIkyxs3jTC@pendragon.ideasonboard.com/ Robert Foss (2): dt-bindings: drm/bridge: anx7625: Revert DPI support Revert "arm64: dts: mt8183: jacuzzi: Fix bus properties in anx's DSI endpoint" .../display/bridge/analogix,anx7625.yaml | 19 +------------------ .../dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 2 -- 2 files changed, 1 insertion(+), 20 deletions(-) -- 2.32.0

3 4

Writeback Assumptions for XRGB
by Maxime Ripard 08 Mar '22

08 Mar '22

Hi, The writeback-check-output is currently broken on vc4. It's in part due to a bug in the kernel driver that results in a page flip timeout, but once that's fixed the test is still broken, and I'm not sure how to solve this one. Indeed, the frame comparison is done between the (XRGB8888) buffer we assign to a plane, and then the buffer we get from the writeback connector. We then run a hashing function on both buffers, and compare the hash, and those hashes won't match. Indeed, while the input buffer uses 0xff for the X component, we'll get back 0x00 from the hardware, and thus the hashes are not identical. We can force the hardware to always set it to 0xff, but that doesn't seem right. It would make more sense to ignore the X component entirely in that case. What do you think?

2 2

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dri-devel March 2022