dri-devel March 2022

dri-devel@lists.freedesktop.org

370 participants
780 discussions

[PATCH v2 00/22] drm: Fill in default values for plane properties
by Maxime Ripard 08 Mar '22

08 Mar '22

Hi, We have a bunch of functions that create planes properties that will take a default value, but it isn't actually enforced in the plane state. This leads to drivers having multiple strategies to work around that issue, most of them being a variation of forcing a value at plane state reset time. Others work fine by luck, or have entirely ignored the issue. This series aims at making sure the default value set by the call to the function isn't ignored, and then making sure all drivers behave consistently. Let me know what you think, Maxime Changes from v1: - Collected tags - Squashed some patches Dave Stevenson (3): drm/object: Add drm_object_property_get_default_value() function drm/object: Add default zpos value at reset drm/object: Add default color encoding and range value at reset Maxime Ripard (19): drm/komeda: plane: switch to plane reset helper drm/tegra: plane: switch to plane reset helper drm/tegra: hub: Fix zpos initial value mismatch drm/omap: plane: Fix zpos initial value mismatch drm/amd/display: Fix color encoding mismatch drm/tegra: plane: Remove redundant zpos initialisation drm/komeda: plane: Remove redundant zpos initialisation drm/exynos: plane: Remove redundant zpos initialisation drm/imx: ipuv3-plane: Remove redundant zpos initialisation drm/msm/mdp5: Remove redundant zpos initialisation drm/nouveau/kms: Remove redundant zpos initialisation drm/omap: plane: Remove redundant zpos initialisation drm/rcar: plane: Remove redundant zpos initialisation drm/sti: plane: Remove redundant zpos initialisation drm/sun4i: layer: Remove redundant zpos initialisation drm/komeda: plane: Remove redundant color encoding and range initialisation drm/armada: overlay: Remove redundant color encoding and range initialisation drm/imx: ipuv3-plane: Remove redundant color encoding and range initialisation drm/omap: plane: Remove redundant color encoding and range initialisation .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../gpu/drm/arm/display/komeda/komeda_plane.c | 13 +---- drivers/gpu/drm/armada/armada_overlay.c | 2 - drivers/gpu/drm/drm_atomic_state_helper.c | 25 +++++++++ drivers/gpu/drm/drm_mode_object.c | 53 +++++++++++++++---- drivers/gpu/drm/exynos/exynos_drm_plane.c | 5 +- drivers/gpu/drm/imx/ipuv3-plane.c | 8 +-- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 16 +++--- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 - drivers/gpu/drm/omapdrm/omap_plane.c | 22 ++++---- drivers/gpu/drm/rcar-du/rcar_du_plane.c | 1 - drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 1 - drivers/gpu/drm/sti/sti_cursor.c | 2 +- drivers/gpu/drm/sti/sti_gdp.c | 2 +- drivers/gpu/drm/sti/sti_hqvdp.c | 2 +- drivers/gpu/drm/sti/sti_plane.c | 6 --- drivers/gpu/drm/sti/sti_plane.h | 1 - drivers/gpu/drm/sun4i/sun4i_layer.c | 16 +++--- drivers/gpu/drm/tegra/hub.c | 2 +- drivers/gpu/drm/tegra/plane.c | 6 +-- include/drm/drm_mode_object.h | 7 +++ 21 files changed, 111 insertions(+), 83 deletions(-) -- 2.35.1

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[PATCH] drm/sun4i: mixer: Fix P010 and P210 format numbers
by Jernej Skrabec 08 Mar '22

08 Mar '22

It turns out that DE3 manual has inverted YUV and YVU format numbers for P010 and P210. Invert them. This was tested by playing video decoded to P010 and additionally confirmed by looking at BSP driver source. Fixes: 169ca4b38932 ("drm/sun4i: Add separate DE3 VI layer formats") Signed-off-by: Jernej Skrabec <jernej.skrabec(a)gmail.com> --- drivers/gpu/drm/sun4i/sun8i_mixer.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index 145833a9d82d..5b3fbee18671 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -111,10 +111,10 @@ /* format 13 is semi-planar YUV411 VUVU */ #define SUN8I_MIXER_FBFMT_YUV411 14 /* format 15 doesn't exist */ -/* format 16 is P010 YVU */ -#define SUN8I_MIXER_FBFMT_P010_YUV 17 -/* format 18 is P210 YVU */ -#define SUN8I_MIXER_FBFMT_P210_YUV 19 +#define SUN8I_MIXER_FBFMT_P010_YUV 16 +/* format 17 is P010 YVU */ +#define SUN8I_MIXER_FBFMT_P210_YUV 18 +/* format 19 is P210 YVU */ /* format 20 is packed YVU444 10-bit */ /* format 21 is packed YUV444 10-bit */ -- 2.35.1

2 1

[PATCH v2 0/8] Prep work for next GuC release
by John.C.Harrison＠Intel.com 08 Mar '22

08 Mar '22

From: John Harrison <John.C.Harrison(a)Intel.com> The next GuC firmware release includes some significant backwards breaking API changes. One such is that there is no longer an LRC descriptor pool. A bunch of prep work for that change can be done in advance - the descriptor pool was being used for things it shouldn't really have been used for anyway. v2: Extend commit message on 'better name' patch. Improve 'split apart' patch to include some necessary re-arrangement that was in a later patch and which introduced an unnecessary conditional in said patch too. (review feedback from Daniele) Signed-off-by: John Harrison <John.C.Harrison(a)Intel.com> John Harrison (8): drm/i915/guc: Do not conflate lrc_desc with GuC id for registration drm/i915/guc: Add an explicit 'submission_initialized' flag drm/i915/guc: Better name for context id limit drm/i915/guc: Split guc_lrc_desc_pin apart drm/i915/guc: Move lrc desc setup to where it is needed drm/i915/guc: Rename desc_idx to ctx_id drm/i915/guc: Drop obsolete H2G definitions drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs drivers/gpu/drm/i915/gt/intel_context.c | 2 +- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 - drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 181 ++++++++++-------- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +- 6 files changed, 109 insertions(+), 84 deletions(-) -- 2.25.1

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[PATCH] backlight: backlight: Slighly simplify devm_of_find_backlight()
by Christophe JAILLET 08 Mar '22

08 Mar '22

Use devm_add_action_or_reset() instead of devm_add_action()+hand writing what is done in the release function, should an error occur. This is more straightforward and saves a few lines of code. While at it, remove a useless test in devm_backlight_release(). 'data' is known to be not NULL when this function is called. Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- drivers/video/backlight/backlight.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c index 4ae6fae94ac2..b788ff3d0f45 100644 --- a/drivers/video/backlight/backlight.c +++ b/drivers/video/backlight/backlight.c @@ -710,8 +710,7 @@ static void devm_backlight_release(void *data) { struct backlight_device *bd = data; - if (bd) - put_device(&bd->dev); + put_device(&bd->dev); } /** @@ -737,11 +736,10 @@ struct backlight_device *devm_of_find_backlight(struct device *dev) bd = of_find_backlight(dev); if (IS_ERR_OR_NULL(bd)) return bd; - ret = devm_add_action(dev, devm_backlight_release, bd); - if (ret) { - put_device(&bd->dev); + ret = devm_add_action_or_reset(dev, devm_backlight_release, bd); + if (ret) return ERR_PTR(ret); - } + return bd; } EXPORT_SYMBOL(devm_of_find_backlight); -- 2.32.0

3 2

[PATCH] drm/i915/dg2: Add preemption changes for Wa_14015141709
by Matt Roper 08 Mar '22

08 Mar '22

From: Akeem G Abodunrin <akeem.g.abodunrin(a)intel.com> Starting with DG2, preemption can no longer be controlled using userspace on a per-context basis. Instead, the hardware only allows us to enable or disable preemption in a global, system-wide basis. Also, we lose the ability to specify the preemption granularity (such as batch-level vs command-level vs object-level). As a result of this - for debugging purposes, this patch adds debugfs interface to configure (disable/enable) preemption globally. Jira: VLK-27831 Cc: Matt Roper <matthew.d.roper(a)intel.com> Cc: Prathap Kumar Valsan <prathap.kumar.valsan(a)intel.com> Cc: John Harrison <john.c.harrison(a)intel.com> Cc: Joonas Lahtinen <joonas.lahtinen(a)linux.intel.com> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin(a)intel.com> Signed-off-by: Matt Roper <matthew.d.roper(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 50 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 3 ++ 4 files changed, 57 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 19cd34f24263..21ede1887b9f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -468,6 +468,9 @@ #define VF_PREEMPTION _MMIO(0x83a4) #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) +#define GEN12_VFG_PREEMPTION_CHICKEN _MMIO(0x83b4) +#define GEN12_VFG_PREEMPT_CHICKEN_DISABLE REG_BIT(8) + #define GEN8_RC6_CTX_INFO _MMIO(0x8504) #define GEN12_SQCM _MMIO(0x8724) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index c014b40d2e9f..18dc82f29776 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2310,7 +2310,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) FF_DOP_CLOCK_GATE_DISABLE); } - if (IS_GRAPHICS_VER(i915, 9, 12)) { + if (HAS_PERCTX_PREEMPT_CTRL(i915)) { /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ wa_masked_en(wal, GEN7_FF_SLICE_CS_CHICKEN1, diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 747fe9f41e1f..40e6e17e2950 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -571,6 +571,55 @@ static int i915_wa_registers(struct seq_file *m, void *unused) return 0; } +static void i915_global_preemption_config(struct drm_i915_private *i915, + u32 val) +{ + const u32 bit = GEN12_VFG_PREEMPT_CHICKEN_DISABLE; + + if (val) + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN, + _MASKED_BIT_DISABLE(bit)); + else + intel_uncore_write(&i915->uncore, GEN12_VFG_PREEMPTION_CHICKEN, + _MASKED_BIT_ENABLE(bit)); +} + +static int i915_global_preempt_support_get(void *data, u64 *val) +{ + struct drm_i915_private *i915 = data; + intel_wakeref_t wakeref; + u32 curr_status = 0; + + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11) + return -EINVAL; + + with_intel_runtime_pm(&i915->runtime_pm, wakeref) + curr_status = intel_uncore_read(&i915->uncore, + GEN12_VFG_PREEMPTION_CHICKEN); + *val = (curr_status & GEN12_VFG_PREEMPT_CHICKEN_DISABLE) ? 0 : 1; + + return 0; +} + +static int i915_global_preempt_support_set(void *data, u64 val) +{ + struct drm_i915_private *i915 = data; + intel_wakeref_t wakeref; + + if (HAS_PERCTX_PREEMPT_CTRL(i915) || GRAPHICS_VER(i915) < 11) + return -EINVAL; + + with_intel_runtime_pm(&i915->runtime_pm, wakeref) + i915_global_preemption_config(i915, val); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_global_preempt_support_fops, + i915_global_preempt_support_get, + i915_global_preempt_support_set, + "%lld\n"); + static int i915_wedged_get(void *data, u64 *val) { struct drm_i915_private *i915 = data; @@ -765,6 +814,7 @@ static const struct i915_debugfs_files { const struct file_operations *fops; } i915_debugfs_files[] = { {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, + {"i915_global_preempt_support", &i915_global_preempt_support_fops}, {"i915_wedged", &i915_wedged_fops}, {"i915_gem_drop_caches", &i915_drop_caches_fops}, #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 457bc1993d19..8c3f69c87d36 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1407,6 +1407,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_GUC_DEPRIVILEGE(dev_priv) \ (INTEL_INFO(dev_priv)->has_guc_deprivilege) +#define HAS_PERCTX_PREEMPT_CTRL(i915) \ + ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) + static inline bool run_as_guest(void) { return !hypervisor_is_type(X86_HYPER_NATIVE); -- 2.34.1

3 4

RE: [PATCH RFC 0/3] MAP_POPULATE for device memory
by David Laight 08 Mar '22

08 Mar '22

From: Christoph Hellwig > Sent: 07 March 2022 15:57 > > On Mon, Mar 07, 2022 at 03:29:35PM +0200, Jarkko Sakkinen wrote: > > So what would you suggest to sort out the issue? I'm happy to go with > > ioctl if nothing else is acceptable. > > PLenty of drivers treat all mmaps as if MAP_POPULATE was specified, > typically by using (io_)remap_pfn_range. If there any reason to only > optionally have the pre-fault semantics for sgx? If not this should > be really simple. And if we have a real need for it to be optional > we'll just need to find a sane way to pass that information to ->mmap. Is there any space in vma->vm_flags ? That would be better than an extra argument or function. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)

2 1

[PATCH v2,0/3] Add mt8186 dsi compatoble & Convert
by xinlei.lee＠mediatek.com 08 Mar '22

08 Mar '22

From: Xinlei Lee <xinlei.lee(a)mediatek.com> V1 title:Add mt8186 dsi compatoble & Move the getting bridge node function The modification is based on avoiding EPROBE_DEFER loop: https://patchwork.kernel.org/project/linux-mediatek/patch/20220131085520.28… Changes since v1: 1. Delete the mediatek,dsi.txt & Add the mediatek,dsi.yaml. 2. Ignore the Move the getting bridge node function patch for V1. Xinlei Lee (3): dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8186 drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c .../display/mediatek/mediatek,dsi.txt | 62 ------------- .../display/mediatek/mediatek,dsi.yaml | 86 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++ 3 files changed, 94 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml -- 2.18.0

3 7

[PATCH] drm/omap: fix NULL but dereferenced coccicheck error
by Wan Jiabing 08 Mar '22

08 Mar '22

Fix the following coccicheck warning: ./drivers/gpu/drm/omapdrm/omap_overlay.c:89:22-25: ERROR: r_ovl is NULL but dereferenced. Here should be ovl->idx rather than r_ovl->idx. Signed-off-by: Wan Jiabing <wanjiabing(a)vivo.com> --- drivers/gpu/drm/omapdrm/omap_overlay.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/omapdrm/omap_overlay.c b/drivers/gpu/drm/omapdrm/omap_overlay.c index 10730c9b2752..b0bc9ad2ef73 100644 --- a/drivers/gpu/drm/omapdrm/omap_overlay.c +++ b/drivers/gpu/drm/omapdrm/omap_overlay.c @@ -86,7 +86,7 @@ int omap_overlay_assign(struct drm_atomic_state *s, struct drm_plane *plane, r_ovl = omap_plane_find_free_overlay(s->dev, overlay_map, caps, fourcc); if (!r_ovl) { - overlay_map[r_ovl->idx] = NULL; + overlay_map[ovl->idx] = NULL; *overlay = NULL; return -ENOMEM; } -- 2.35.1

2 1

[PATCH v13 00/22] Add MediaTek SoC DRM (vdosys1) support for mt8195
by Nancy.Lin 08 Mar '22

08 Mar '22

The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, OVL_ADAPTOR and MERGE. Add DRM and these modules support by the patches below: Changes in v13: - fix reviewer comment in v12 - fix rdma dt-binding format - fix dts node naming - fix 32 bit build error - modify 64bit dependency for mtk-mmsys - rebase to vdosys0 series v16. (ref [5]) Changes in v12: - fix reviewer comment in v11 - modify mbox index - refine dma dev for ovl_adaptor sub driver Changes in v11: - remove ethdr vblank spin lock - refine ovl_adaptor print message Changes in v10: - refine ethdr reset control using devm_reset_control_array_get_optional_exclusive - fix ovl_adaptor mtk_ovl_adaptor_clk_enable error handle issue Changes in v9: - rebase on kernel-5.16-rc1 - rebase on vdosys0 series v13. (ref [5]) - fix ovl_adaptor sub driver is brought up unintentionally - fix clang build test fail- duplicate ethdr/mdp_rdma init_module/cleanup_module symbol issue Changes in v8: - separate merge async reset to new patch. - separate drm ovl_adaptor sub driver to new patch. - fix reviewer comment in v7. Changes in v7: - rebase on vdosys0 series v12 (ref[5]) - add dma description in ethdr binding document. - refine vdosys1 bit definition of mmsys routing table. - separate merge modification into 3 pathces. - separate mutex modification into 2 patches. - add plane color coding for mdp_rdma csc. - move mdp_rdma pm control to ovl_adaptor. - fix reviewer comment in v6. Changes in v6: - rebase on kernel-5.15-rc1. - change mbox label to gce0 for dts node of vdosys1. - modify mmsys reset num for mt8195. - rebase on vdosys0 series v10. (ref [5]) - use drm to bring up ovl_adaptor driver. - move drm iommu/mutex check from kms init to drm bind. - modify rdma binding doc location. (Documentation/devicetree/bindings/arm/) - modify for reviewer's comment in v5. Changes in v5: - add mmsys reset controller reference. Changes in v4: - use merge common driver for merge1~4. - refine ovl_adaptor rdma driver. - use ovl_adaptor ddp_comp function instead of ethdr. - modify for reviewer's comment in v3. Changes in v3: - modify for reviewer's comment in v2. - add vdosys1 2 pixels align limit. - add mixer odd offset support. Changes in v2: - Merge PSEUDO_OVL and ETHDR into one DRM component. - Add mmsys config API for vdosys1 hardware setting. - Add mmsys reset control using linux reset framework. Signed-off-by: Nancy.Lin <nancy.lin(a)mediatek.com> This series are based on the following patch: [1] arm64: dts: Add mediatek SoC mt8195 and evaluation board https://patchwork.kernel.org/project/linux-mediatek/patch/20220112114724.19… [2] arm64: dts: mt8195: add IOMMU and smi nodes https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26… [3] arm64: dts: mt8195: add gce node https://patchwork.kernel.org/project/linux-mediatek/patch/20220126090109.32… [4] [v2] arm64: dts: mt8195: add display node for vdosys0 https://patchwork.kernel.org/project/linux-mediatek/patch/20220225021535.26… [5] Add MediaTek SoC DRM (vdosys0) support for mt8195 https://patchwork.kernel.org/project/linux-mediatek/list/?series=620795 Nancy.Lin (22): dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 dt-bindings: reset: mt8195: add vdosys1 reset control bit soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 soc: mediatek: mmsys: Specify 64BIT dependency for MTK_MMSYS soc: mediatek: change the mutex defines and the mutex_mod type soc: mediatek: add mtk-mutex support for mt8195 vdosys1 drm/mediatek: add display MDP RDMA support for MT8195 drm/mediatek: add display merge advance config API for MT8195 drm/mediatek: add display merge start/stop API for cmdq support drm/mediatek: add display merge mute/unmute support for MT8195 drm/mediatek: add display merge async reset control drm/mediatek: add ETHDR support for MT8195 drm/mediatek: add mediatek-drm plane color encoding info drm/mediatek: add ovl_adaptor support for MT8195 drm/mediatek: add dma dev get function drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support drm/mediatek: add drm ovl_adaptor sub driver for MT8195 drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 arm64: dts: mt8195: add display node for vdosys1 .../arm/mediatek/mediatek,mdp-rdma.yaml | 86 ++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 223 +++++++++ drivers/gpu/drm/mediatek/Makefile | 5 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 29 ++ drivers/gpu/drm/mediatek/mtk_disp_merge.c | 89 +++- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 443 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 55 ++- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 31 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 329 +++++++++---- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 13 +- drivers/gpu/drm/mediatek/mtk_drm_plane.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_plane.h | 1 + drivers/gpu/drm/mediatek/mtk_ethdr.c | 376 +++++++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 23 + drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 315 +++++++++++++ drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 20 + drivers/soc/mediatek/Kconfig | 1 + drivers/soc/mediatek/mt8195-mmsys.h | 199 ++++++++ drivers/soc/mediatek/mtk-mmsys.c | 79 +++- drivers/soc/mediatek/mtk-mmsys.h | 11 + drivers/soc/mediatek/mtk-mutex.c | 318 +++++++------ include/dt-bindings/reset/mt8195-resets.h | 12 + include/linux/soc/mediatek/mtk-mmsys.h | 22 + 25 files changed, 2439 insertions(+), 255 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h -- 2.18.0

1 22

[PATCH v1 0/2] Revert vendor property from anx7625 bindings
by Robert Foss 08 Mar '22

08 Mar '22

An issue[1] related to how the V4L2_FWNODE_BUS_TYPE_PARALLEL flag is mis-used was found in recent addition to the anx7625 driver. In order to not introduce this issue into the ABI, let's revert the changes to the anx7625 dt-binding related to this. [1] https://lore.kernel.org/all/YiTruiCIkyxs3jTC@pendragon.ideasonboard.com/ Robert Foss (2): Revert "dt-bindings:drm/bridge:anx7625:add vendor define" Revert "arm64: dts: mt8183: jacuzzi: Fix bus properties in anx's DSI endpoint" .../display/bridge/analogix,anx7625.yaml | 65 +------------------ .../dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 2 - 2 files changed, 2 insertions(+), 65 deletions(-) -- 2.32.0

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dri-devel March 2022