dri-devel February 2020

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679 discussions

[PATCH] drm/pl111: Support Integrator IM-PD1 module
by Linus Walleij 14 Feb '20

14 Feb '20

The last in-kernel user of the old framebuffer driver is the IM-PD1 module for the Integrator/AP. Let's implement support for this remaining user so we can migrate the last user over to DRM and delete the old FB driver. On the Integrator/AP the IM-PD1 system controller will exist alongside the common Integrator system controller so make sure to do a special lookup for the IM-PD1 syscon and make it take precedence if found. Tested on the Integrator/AP with the IM-PD1 mounted. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- drivers/gpu/drm/pl111/pl111_versatile.c | 73 +++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/gpu/drm/pl111/pl111_versatile.c b/drivers/gpu/drm/pl111/pl111_versatile.c index 09aeaffb7660..4f325c410b5d 100644 --- a/drivers/gpu/drm/pl111/pl111_versatile.c +++ b/drivers/gpu/drm/pl111/pl111_versatile.c @@ -19,6 +19,7 @@ static struct regmap *versatile_syscon_map; * We detect the different syscon types from the compatible strings. */ enum versatile_clcd { + INTEGRATOR_IMPD1, INTEGRATOR_CLCD_CM, VERSATILE_CLCD, REALVIEW_CLCD_EB, @@ -65,6 +66,14 @@ static const struct of_device_id versatile_clcd_of_match[] = { {}, }; +static const struct of_device_id impd1_clcd_of_match[] = { + { + .compatible = "arm,im-pd1-syscon", + .data = (void *)INTEGRATOR_IMPD1, + }, + {}, +}; + /* * Core module CLCD control on the Integrator/CP, bits * 8 thru 19 of the CM_CONTROL register controls a bunch @@ -125,6 +134,36 @@ static void pl111_integrator_enable(struct drm_device *drm, u32 format) val); } +#define IMPD1_CTRL_OFFSET 0x18 +#define IMPD1_CTRL_DISP_LCD (0 << 0) +#define IMPD1_CTRL_DISP_VGA (1 << 0) +#define IMPD1_CTRL_DISP_LCD1 (2 << 0) +#define IMPD1_CTRL_DISP_ENABLE (1 << 2) +#define IMPD1_CTRL_DISP_MASK (7 << 0) + +static void pl111_impd1_enable(struct drm_device *drm, u32 format) +{ + u32 val; + + dev_info(drm->dev, "enable IM-PD1 CLCD connectors\n"); + val = IMPD1_CTRL_DISP_VGA | IMPD1_CTRL_DISP_ENABLE; + + regmap_update_bits(versatile_syscon_map, + IMPD1_CTRL_OFFSET, + IMPD1_CTRL_DISP_MASK, + val); +} + +static void pl111_impd1_disable(struct drm_device *drm) +{ + dev_info(drm->dev, "disable IM-PD1 CLCD connectors\n"); + + regmap_update_bits(versatile_syscon_map, + IMPD1_CTRL_OFFSET, + IMPD1_CTRL_DISP_MASK, + 0); +} + /* * This configuration register in the Versatile and RealView * family is uniformly present but appears more and more @@ -270,6 +309,20 @@ static const struct pl111_variant_data pl110_integrator = { .fb_bpp = 16, }; +/* + * The IM-PD1 variant is a PL110 with a bunch of broken, or not + * yet implemented features + */ +static const struct pl111_variant_data pl110_impd1 = { + .name = "PL110 IM-PD1", + .is_pl110 = true, + .broken_clockdivider = true, + .broken_vblank = true, + .formats = pl110_integrator_pixel_formats, + .nformats = ARRAY_SIZE(pl110_integrator_pixel_formats), + .fb_bpp = 16, +}; + /* * This is the in-between PL110 variant found in the ARM Versatile, * supporting RGB565/BGR565 @@ -322,8 +375,21 @@ int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv) /* Non-ARM reference designs, just bail out */ return 0; } + versatile_clcd_type = (enum versatile_clcd)clcd_id->data; + /* + * On the Integrator, check if we should use the IM-PD1 instead, + * if we find it, it will take precedence. This is on the Integrator/AP + * which only has this option for PL110 graphics. + */ + if (versatile_clcd_type == INTEGRATOR_CLCD_CM) { + np = of_find_matching_node_and_match(NULL, impd1_clcd_of_match, + &clcd_id); + if (np) + versatile_clcd_type = (enum versatile_clcd)clcd_id->data; + } + /* Versatile Express special handling */ if (versatile_clcd_type == VEXPRESS_CLCD_V2M) { struct platform_device *pdev; @@ -367,6 +433,13 @@ int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv) priv->variant_display_enable = pl111_integrator_enable; dev_info(dev, "set up callbacks for Integrator PL110\n"); break; + case INTEGRATOR_IMPD1: + versatile_syscon_map = map; + priv->variant = &pl110_impd1; + priv->variant_display_enable = pl111_impd1_enable; + priv->variant_display_disable = pl111_impd1_disable; + dev_info(dev, "set up callbacks for IM-PD1 PL110\n"); + break; case VERSATILE_CLCD: versatile_syscon_map = map; /* This can do RGB565 with external PLD */ -- 2.23.0

2 2

Re: Re: [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver support
by chandanu＠codeaurora.org 14 Feb '20

14 Feb '20

Hello Rob, We removed the bridge object for DisplayPort due to review comments in patch set 1. Added more details below. > -------- Original Message -------- > Subject: Re: [DPU PATCH v3 3/5] drm/msm/dp: add displayPort driver > support > Date: 2019-12-02 08:48 > From: Rob Clark <robdclark(a)gmail.com> > To: Chandan Uddaraju <chandanu(a)codeaurora.org> > Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" > <devicetree(a)vger.kernel.org>, linux-arm-msm > <linux-arm-msm(a)vger.kernel.org>, Abhinav Kumar > <abhinavk(a)codeaurora.org>, Sean Paul <seanpaul(a)chromium.org>, > dri-devel <dri-devel(a)lists.freedesktop.org>, "Kristian H. Kristensen" > <hoegsberg(a)google.com>, freedreno <freedreno(a)lists.freedesktop.org> > > On Mon, Dec 2, 2019 at 5:48 AM Chandan Uddaraju > <chandanu(a)codeaurora.org> wrote: >> >> Add the needed displayPort files to enable DP driver >> on msm target. >> >> "dp_display" module is the main module that calls into >> other sub-modules. "dp_drm" file represents the interface >> between DRM framework and DP driver. >> >> changes in v2: >> -- Update copyright markings on all relevant files. >> -- Change pr_err() to DRM_ERROR() >> -- Use APIs directly instead of function pointers. >> -- Use drm_display_mode structure to store link parameters in the >> driver. >> -- Use macros for register definitions instead of hardcoded values. >> -- Replace writel_relaxed/readl_relaxed with writel/readl >> and remove memory barriers. >> -- Remove unnecessary NULL checks. >> -- Use drm helper functions for dpcd read/write. >> -- Use DRM_DEBUG_DP for debug msgs. >> >> changes in V3: >> -- Removed changes in dpu_io_util.[ch] >> -- Added locking around "is_connected" flag and removed atomic_set() >> -- Removed the argument validation checks in all the static functions >> except initialization functions and few API calls across msm/dp >> files >> -- Removed hardcoded values for register reads/writes >> -- Removed vreg related generic structures. >> -- Added return values where ever necessary. >> -- Updated dp_ctrl_on function. >> -- Calling the ctrl specific catalog functions directly instead of >> function pointers. >> -- Added seperate change that adds standard value in drm_dp_helper >> file. >> -- Added separate change in this list that is used to initialize >> displayport in DPU driver. >> -- Added change to use drm_dp_get_adjust_request_voltage() function. >> >> Signed-off-by: Chandan Uddaraju <chandanu(a)codeaurora.org> >> --- > > [snip] > >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> index f96e142..29ac7d3 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> @@ -967,6 +967,9 @@ static void dpu_encoder_virt_mode_set(struct >> drm_encoder *drm_enc, >> >> trace_dpu_enc_mode_set(DRMID(drm_enc)); >> >> + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && >> priv->dp) >> + msm_dp_display_mode_set(priv->dp, drm_enc, mode, >> adj_mode); >> + > > for better or for worse, DSI and HDMI backends create an internal > drm_bridge object to avoid all of these shunts over from the encoder. > We might be still the only driver to do this, but IMHO it is better > than making each encoder know about each backend, so we might as well > stick with that. > > (same goes for the other 'if (drm_enc->encoder_type == > DRM_MODE_ENCODER_TMDS)'s) > We had the below comments from Sean Paul to remove the bridge object in patch set 1 of this change. ********** ****************** > +static const struct drm_bridge_funcs dp_bridge_ops = { > + .mode_fixup = dp_bridge_mode_fixup, > + .pre_enable = dp_bridge_pre_enable, > + .enable = dp_bridge_enable, > + .disable = dp_bridge_disable, > + .post_disable = dp_bridge_post_disable, > + .mode_set = dp_bridge_mode_set, > +}; I'm not convinced you need any of this. The only advantage a bridge gets you is to be involved in modeset. However the only thing you do in modeset is save the mode (which is only used in enable). So why not just use the mode from the crtc's state when encoder->enable is called? That allows you to delete all of the bridge stuff here. > + > +int dp_connector_post_init(struct drm_connector *connector, void > *display) > +{ > + struct msm_dp *dp_display = display; > + > + if (!dp_display) > + return -EINVAL; ******************************* **************** thanks Chandan > BR, > -R > > >> list_for_each_entry(conn_iter, connector_list, head) >> if (conn_iter->encoder == drm_enc) >> conn = conn_iter; > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

1 0

[PATCH] drm/mm: Break long searches in fragmented address spaces
by Chris Wilson 14 Feb '20

14 Feb '20

We try hard to select a suitable hole in the drm_mm first time. But if that is unsuccessful, we then have to look at neighbouring nodes, and this requires traversing the rbtree. Walking the rbtree can be slow (much slower than a linear list for deep trees), and if the drm_mm has been purposefully fragmented our search can be trapped for a long, long time. For non-preemptible kernels, we need to break up long CPU bound sections by manually checking for cond_resched(); similarly we should also bail out if we have been told to terminate. (In an ideal world, we would break for any signal, but we need to trade off having to perform the search again after ERESTARTSYS, which again may form a trap of making no forward progress.) Reported-by: Zbigniew Kempczyński <zbigniew.kempczynski(a)intel.com> Signed-off-by: Chris Wilson <chris(a)chris-wilson.co.uk> Cc: Zbigniew Kempczyński <zbigniew.kempczynski(a)intel.com> Cc: Joonas Lahtinen <joonas.lahtinen(a)linux.intel.com> --- drivers/gpu/drm/drm_mm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 2a6e34663146..47d5de9ca0a8 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -45,6 +45,7 @@ #include <linux/export.h> #include <linux/interval_tree_generic.h> #include <linux/seq_file.h> +#include <linux/sched/signal.h> #include <linux/slab.h> #include <linux/stacktrace.h> @@ -366,6 +367,11 @@ next_hole(struct drm_mm *mm, struct drm_mm_node *node, enum drm_mm_insert_mode mode) { + /* Searching is slow; check if we ran out of time/patience */ + cond_resched(); + if (fatal_signal_pending(current)) + return NULL; + switch (mode) { default: case DRM_MM_INSERT_BEST: @@ -557,7 +563,7 @@ int drm_mm_insert_node_in_range(struct drm_mm * const mm, return 0; } - return -ENOSPC; + return signal_pending(current) ? -ERESTARTSYS : -ENOSPC; } EXPORT_SYMBOL(drm_mm_insert_node_in_range); -- 2.25.0

2 2

[PATCH] nouveau: no need to check return value of debugfs_create functions
by Greg Kroah-Hartman 13 Feb '20

13 Feb '20

When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Ben Skeggs <bskeggs(a)redhat.com> Cc: David Airlie <airlied(a)linux.ie> Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: dri-devel(a)lists.freedesktop.org Cc: nouveau(a)lists.freedesktop.org Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> --- drivers/gpu/drm/nouveau/nouveau_debugfs.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index 080e964d49aa..d1c82fc45a68 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c @@ -224,14 +224,10 @@ nouveau_drm_debugfs_init(struct drm_minor *minor) struct dentry *dentry; int i; - for (i = 0; i < ARRAY_SIZE(nouveau_debugfs_files); i++) { - dentry = debugfs_create_file(nouveau_debugfs_files[i].name, - S_IRUGO | S_IWUSR, - minor->debugfs_root, minor->dev, - nouveau_debugfs_files[i].fops); - if (!dentry) - return -ENOMEM; - } + for (i = 0; i < ARRAY_SIZE(nouveau_debugfs_files); i++) + debugfs_create_file(nouveau_debugfs_files[i].name, + S_IRUGO | S_IWUSR, minor->debugfs_root, + minor->dev, nouveau_debugfs_files[i].fops); drm_debugfs_create_files(nouveau_debugfs_list, NOUVEAU_DEBUGFS_ENTRIES, -- 2.25.0

4 6

[PATCH] drm/i915: Disable -Wtautological-constant-out-of-range-compare
by Nathan Chancellor 13 Feb '20

13 Feb '20

A recent commit in clang added -Wtautological-compare to -Wall, which is enabled for i915 so we see the following warning: ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1485:22: warning: result of comparison of constant 576460752303423487 with expression of type 'unsigned int' is always false [-Wtautological-constant-out-of-range-compare] if (unlikely(remain > N_RELOC(ULONG_MAX))) ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~ This warning only happens on x86_64 but that check is relevant for 32-bit x86 so we cannot remove it. -Wtautological-compare on a whole has good warnings but this one is not really relevant for the kernel because of all of the different configurations that are used to build the kernel. When -Wtautological-compare is enabled for the kernel, this option will remain disabled so do that for i915 now. Link: https://github.com/ClangBuiltLinux/linux/issues/778 Signed-off-by: Nathan Chancellor <natechancellor(a)gmail.com> --- drivers/gpu/drm/i915/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 38df01c23176..55dbcca179c7 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -21,6 +21,7 @@ subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable) subdir-ccflags-y += $(call cc-disable-warning, sign-compare) subdir-ccflags-y += $(call cc-disable-warning, sometimes-uninitialized) subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides) +subdir-ccflags-y += $(call cc-disable-warning, tautological-constant-out-of-range-compare) subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror # Fine grained warnings disable -- 2.25.0

4 11

[PATCH] drm/msm/dpu: fix BGR565 vs RGB565 confusion
by Rob Clark 13 Feb '20

13 Feb '20

From: Rob Clark <robdclark(a)chromium.org> The component order between the two was swapped, resulting in incorrect color when games with 565 visual hit the overlay path instead of GPU composition. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Rob Clark <robdclark(a)chromium.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 24ab6249083a..6f420cc73dbd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -255,13 +255,13 @@ static const struct dpu_format dpu_format_map[] = { INTERLEAVED_RGB_FMT(RGB565, 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3, + C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3, false, 2, 0, DPU_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(BGR565, 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3, + C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3, false, 2, 0, DPU_FETCH_LINEAR, 1), -- 2.24.1

2 1

[resend PATCH v6 00/12] arm/arm64: mediatek: Fix mmsys device probing
by matthias.bgg＠kernel.org 13 Feb '20

13 Feb '20

From: Matthias Brugger <mbrugger(a)suse.com> [reseding due to wrong mail of Stephen] This is version five of the series. It's a long time this wasn't worked on, so as a reminder, version four can be found here: https://patchwork.kernel.org/cover/10686247/ The biggest changes this new version does, is to implement the clock probing through a platform driver. The corresponding platform device get's created in the DRM driver. I converted all the clock drivers to platform drivers and tested the approach on the Acer Chromebook R13 (mt8173 based). Apart from that I reordered the patches so that the DT bindings update are the first patches. Changes since v5: - re-arrange the patch order - generate platform_device for mmsys clock driver inside the DRM driver - fix DTS binding accordingly - switch all mmsys clock driver to platform probing - fix mt8173 platform driver remove function - fix probe defer path in HDMI driver - fix probe defer path in mtk_mdp_comp - fix identation of error messages Changes since v4: - fix missing regmap accessors in drm diver (patch 1) - omit probe deffered warning on all drivers (patch 5) - update drm and clk bindings (patch 6 and 7) - put mmsys clock part in dts child node of mmsys. Only done for HW where no dts backport compatible breakage is expected (either DRM driver not yet implemented or no HW available to the public) (patch 9 to 12) Changes since v3: - use platform device to probe clock driver - add Acked-by CK Hu for the probe deferred patch Changes since v2: - fix kconfig typo (shame on me) - delete __initconst from mm_clocks as converted to a platform driver Changes since v1: - add binding documentation - ddp: use regmap_update_bits - ddp: ignore EPROBE_DEFER on clock probing - mfd: delete mmsys_private - add Reviewed-by and Acked-by tags MMSYS in Mediatek SoCs has some registers to control clock gates (which is used in the clk driver) and some registers to set the routing and enable the differnet blocks of the display subsystem. Up to now both drivers, clock and drm are probed with the same device tree compatible. But only the first driver get probed, which in effect breaks graphics on mt8173 and mt2701. This patch uses a platform device registration in the DRM driver, which will trigger the probe of the corresponding clock driver. It was tested on the bananapi-r2 and the Acer R13 Chromebook. Matthias Brugger (12): dt-bindings: display: mediatek: Add mmsys binding description dt-bindings: mediatek: Add compatible for mt7623 drm/mediatek: Use regmap for register access drm: mediatek: Omit warning on probe defers media: mtk-mdp: Check return value of of_clk_get clk: mediatek: mt2701: switch mmsys to platform device probing clk: mediatek: mt2712e: switch to platform device probing clk: mediatek: mt6779: switch mmsys to platform device probing clk: mediatek: mt6797: switch to platform device probing clk: mediatek: mt8183: switch mmsys to platform device probing clk: mediatek: mt8173: switch mmsys to platform device probing drm/mediatek: Add support for mmsys through a pdev .../display/mediatek/mediatek,disp.txt | 30 ++++++----- drivers/clk/mediatek/clk-mt2701-mm.c | 41 +++++++++----- drivers/clk/mediatek/clk-mt2712-mm.c | 39 +++++++++----- drivers/clk/mediatek/clk-mt6779-mm.c | 41 +++++++++----- drivers/clk/mediatek/clk-mt6797-mm.c | 43 ++++++++++----- drivers/clk/mediatek/clk-mt8173.c | 51 +++++++++++++++--- drivers/clk/mediatek/clk-mt8183-mm.c | 39 +++++++++----- drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 +- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 5 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 +++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 54 +++++++++---------- drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 35 +++++++++--- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 4 +- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++- drivers/gpu/drm/mediatek/mtk_hdmi.c | 4 +- drivers/media/platform/mtk-mdp/mtk_mdp_comp.c | 6 +++ 19 files changed, 295 insertions(+), 135 deletions(-) -- 2.24.0

5 33

[PATCH v3] drm/tidss: dispc: Rewrite naive plane positioning code
by Jyri Sarha 13 Feb '20

13 Feb '20

The old implementation of placing planes on the CRTC while configuring the planes was naive and relied on the order in which the planes were configured, enabled, and disabled. The situation where a plane's zpos was changed on the fly was completely broken. The usual symptoms of this problem was scrambled display and a flood of sync lost errors, when a plane was active in two layers at the same time, or a missing plane, in case when a layer was accidentally disabled. The rewrite takes a more straight forward approach when HW is concerned. The plane positioning registers are in the CRTC (or actually OVR) register space and it is more natural to configure them in a one go when configuring the CRTC. To do this we need make sure we have all the planes on the updated CRTCs in the new atomic state. The untouched planes on changed CRTCs are added to the atomic state in tidss_atomic_check(). Signed-off-by: Jyri Sarha <jsarha(a)ti.com> --- drivers/gpu/drm/tidss/tidss_crtc.c | 52 +++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.c | 55 +++++++++++------------------ drivers/gpu/drm/tidss/tidss_dispc.h | 5 +++ drivers/gpu/drm/tidss/tidss_kms.c | 33 ++++++++++++++++- 4 files changed, 109 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c index 032c31ee2820..36478c54784b 100644 --- a/drivers/gpu/drm/tidss/tidss_crtc.c +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -17,6 +17,7 @@ #include "tidss_dispc.h" #include "tidss_drv.h" #include "tidss_irq.h" +#include "tidss_plane.h" /* Page flip and frame done IRQs */ @@ -111,6 +112,53 @@ static int tidss_crtc_atomic_check(struct drm_crtc *crtc, return dispc_vp_bus_check(dispc, hw_videoport, state); } +/* + * This needs all affected planes to be present in the atomic + * state. The untouched planes are added to the state in + * tidss_atomic_check(). + */ +static void tidss_crtc_position_planes(struct tidss_device *tidss, + struct drm_crtc *crtc, + struct drm_crtc_state *old_state, + bool newmodeset) +{ + struct drm_atomic_state *ostate = old_state->state; + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + struct drm_crtc_state *cstate = crtc->state; + int zpos; + + if (!newmodeset && !cstate->zpos_changed && !cstate->planes_changed) + return; + + for (zpos = 0; zpos < tidss->feat->num_planes; zpos++) { + struct drm_plane_state *pstate; + struct drm_plane *plane; + bool zpos_taken = false; + int i; + + for_each_new_plane_in_state(ostate, plane, pstate, i) { + if (pstate->crtc != crtc || !pstate->visible) + continue; + + if (pstate->normalized_zpos == zpos) { + zpos_taken = true; + break; + } + } + + if (zpos_taken) { + struct tidss_plane *tplane = to_tidss_plane(plane); + + dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id, + tcrtc->hw_videoport, + pstate->crtc_x, pstate->crtc_y, + zpos); + } + dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, zpos, + zpos_taken); + } +} + static void tidss_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { @@ -146,6 +194,9 @@ static void tidss_crtc_atomic_flush(struct drm_crtc *crtc, /* Write vp properties to HW if needed. */ dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false); + /* Update plane positions if needed. */ + tidss_crtc_position_planes(tidss, crtc, old_crtc_state, false); + WARN_ON(drm_crtc_vblank_get(crtc) != 0); spin_lock_irqsave(&ddev->event_lock, flags); @@ -183,6 +234,7 @@ static void tidss_crtc_atomic_enable(struct drm_crtc *crtc, return; dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, true); + tidss_crtc_position_planes(tidss, crtc, old_state, true); /* Turn vertical blanking interrupt reporting on. */ drm_crtc_vblank_on(crtc); diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index eeb160dc047b..e79dad246b1e 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -281,11 +281,6 @@ struct dss_vp_data { u32 *gamma_table; }; -struct dss_plane_data { - u32 zorder; - u32 hw_videoport; -}; - struct dispc_device { struct tidss_device *tidss; struct device *dev; @@ -307,8 +302,6 @@ struct dispc_device { struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; - struct dss_plane_data plane_data[TIDSS_MAX_PLANES]; - u32 *fourccs; u32 num_fourccs; @@ -1247,7 +1240,7 @@ int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, /* OVR */ static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, - u32 x, u32 y, u32 zpos) + u32 x, u32 y, u32 layer) { /* On k2g there is only one plane and no need for ovr */ dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION, @@ -1256,44 +1249,43 @@ static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc, static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, - u32 x, u32 y, u32 zpos) + u32 x, u32 y, u32 layer) { - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), hw_plane, 4, 1); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, 17, 6); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y, 30, 19); } static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, - u32 x, u32 y, u32 zpos) + u32 x, u32 y, u32 layer) { - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), hw_plane, 4, 1); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(zpos), + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x, 13, 0); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(zpos), + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y, 29, 16); } -static void dispc_ovr_set_plane(struct dispc_device *dispc, - u32 hw_plane, u32 hw_videoport, - u32 x, u32 y, u32 zpos) +void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, + u32 hw_videoport, u32 x, u32 y, u32 layer) { switch (dispc->feat->subrev) { case DISPC_K2G: dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, - x, y, zpos); + x, y, layer); break; case DISPC_AM65X: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, - x, y, zpos); + x, y, layer); break; case DISPC_J721E: dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport, - x, y, zpos); + x, y, layer); break; default: WARN_ON(1); @@ -1301,10 +1293,13 @@ static void dispc_ovr_set_plane(struct dispc_device *dispc, } } -static void dispc_ovr_enable_plane(struct dispc_device *dispc, - u32 hw_videoport, u32 zpos, bool enable) +void dispc_ovr_enable_layer(struct dispc_device *dispc, + u32 hw_videoport, u32 layer, bool enable) { - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + if (dispc->feat->subrev == DISPC_K2G) + return; + + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), !!enable, 0, 0); } @@ -2070,21 +2065,11 @@ int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, 28, 28); - dispc_ovr_set_plane(dispc, hw_plane, hw_videoport, - state->crtc_x, state->crtc_y, - state->normalized_zpos); - - dispc->plane_data[hw_plane].zorder = state->normalized_zpos; - dispc->plane_data[hw_plane].hw_videoport = hw_videoport; - return 0; } int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { - dispc_ovr_enable_plane(dispc, dispc->plane_data[hw_plane].hw_videoport, - dispc->plane_data[hw_plane].zorder, enable); - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); return 0; diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index e65e6a2bb821..a4a68249e44b 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -94,6 +94,11 @@ extern const struct dispc_features dispc_j721e_feats; void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask); dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc); +void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, + u32 hw_videoport, u32 x, u32 y, u32 layer); +void dispc_ovr_enable_layer(struct dispc_device *dispc, + u32 hw_videoport, u32 layer, bool enable); + void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state); void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c index 5311e0f1c551..ae461cabff4c 100644 --- a/drivers/gpu/drm/tidss/tidss_kms.c +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -47,9 +47,40 @@ static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { .atomic_commit_tail = tidss_atomic_commit_tail, }; +static int tidss_atomic_check(struct drm_device *ddev, + struct drm_atomic_state *state) +{ + struct drm_crtc_state *cstate; + struct drm_crtc *crtc; + int ret, i; + + ret = drm_atomic_helper_check(ddev, state); + if (ret) + return ret; + + /* + * If a plane on a CRTC changes add all active planes on that + * CRTC to the atomic state. This is needed for updating the + * plane positions in tidss_crtc_position_planes() which is + * called from crtc_atomic_enable() and crtc_atomic_flush(). + * The update is needed for x,y-position changes too, so + * zpos_changed condition is not enough and we need this if + * planes_changed is true too. + */ + for_each_new_crtc_in_state(state, crtc, cstate, i) { + if (cstate->zpos_changed || cstate->planes_changed) { + ret = drm_atomic_add_affected_planes(state, crtc); + if (ret) + return ret; + } + } + + return 0; +} + static const struct drm_mode_config_funcs mode_config_funcs = { .fb_create = drm_gem_fb_create, - .atomic_check = drm_atomic_helper_check, + .atomic_check = tidss_atomic_check, .atomic_commit = drm_atomic_helper_commit, }; -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

2 3

[PATCH v3 0/4] drm/virtio: rework batching
by Gerd Hoffmann 13 Feb '20

13 Feb '20

v4: - split into multiple patches. Gerd Hoffmann (4): drm/virtio: rework notification for better batching drm/virtio: batch plane updates (pageflip) drm/virtio: batch resource creation drm/virtio: batch display query. drivers/gpu/drm/virtio/virtgpu_drv.h | 6 ++-- drivers/gpu/drm/virtio/virtgpu_display.c | 2 ++ drivers/gpu/drm/virtio/virtgpu_ioctl.c | 1 + drivers/gpu/drm/virtio/virtgpu_kms.c | 2 ++ drivers/gpu/drm/virtio/virtgpu_object.c | 1 + drivers/gpu/drm/virtio/virtgpu_plane.c | 7 ++-- drivers/gpu/drm/virtio/virtgpu_vq.c | 41 +++++++++++++----------- 7 files changed, 33 insertions(+), 27 deletions(-) -- 2.18.2

2 6

[PATCH] drm/atmel-hlcdc: set layer REP bit to enable replication logic
by Joshua.Henderson＠microchip.com 13 Feb '20

13 Feb '20

This bit enables replication logic to expand an RGB color less than 24 bits, to 24 bits, which is used internally for all formats. Otherwise, the least significant bits are always set to zero and the color may not be what is expected. Signed-off-by: Joshua Henderson <joshua.henderson(a)microchip.com> --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index eb7c4cf..6f6cf61 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -389,7 +389,7 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG, cfg); - cfg = ATMEL_HLCDC_LAYER_DMA; + cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP; if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) { cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL | -- 2.7.4

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dri-devel February 2020