dri-devel February 2020

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302 participants
679 discussions

[PATCH v2 0/3] ASoC: mediatek: mt8173-rt5650: HDMI jack reporting
by Tzung-Bi Shih 13 Feb '20

13 Feb '20

The series supports HDMI jack reporting to mt8173-rt5650. The 1st patch is less related. It stops running in probe() if failed to register audio driver. The 2nd patch supports jack reporting in DRM driver. The 3rd patch supports jack reporting in mt8173-rt5650 ASoC machine driver. Changes from v1: - refactor the 2nd patch to simplify the code Tzung-Bi Shih (3): drm/mediatek: exit earlier if failed to register audio driver drm/mediatek: support HDMI jack status reporting ASoC: mediatek: mt8173-rt5650: support HDMI jack reporting drivers/gpu/drm/mediatek/mtk_hdmi.c | 45 ++++++++++++++++++++--- sound/soc/mediatek/mt8173/mt8173-rt5650.c | 17 ++++++++- 2 files changed, 55 insertions(+), 7 deletions(-) -- 2.25.0.341.g760bfbb309-goog

3 11

[drm-intel:drm-intel-next-queued 5/5] drivers/gpu/drm/i915/gt/intel_lrc.c:2335:16: error: unused variable 'regs'
by kbuild test robot 13 Feb '20

13 Feb '20

tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued head: c616d2387aeeb987f03eee848f04ffdc248c7aae commit: c616d2387aeeb987f03eee848f04ffdc248c7aae [5/5] drm/i915/gt: Expand bad CS completion event debug config: i386-randconfig-h003-20200213 (attached as .config) compiler: gcc-7 (Debian 7.5.0-4) 7.5.0 reproduce: git checkout c616d2387aeeb987f03eee848f04ffdc248c7aae # save the attached .config to linux build tree make ARCH=i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp(a)intel.com> All errors (new ones prefixed by >>): drivers/gpu/drm/i915/gt/intel_lrc.c: In function 'process_csb': >> drivers/gpu/drm/i915/gt/intel_lrc.c:2335:16: error: unused variable 'regs' [-Werror=unused-variable] const u32 *regs = rq->context->lrc_reg_state; ^~~~ cc1: all warnings being treated as errors vim +/regs +2335 drivers/gpu/drm/i915/gt/intel_lrc.c 2222 2223 static void process_csb(struct intel_engine_cs *engine) 2224 { 2225 struct intel_engine_execlists * const execlists = &engine->execlists; 2226 const u32 * const buf = execlists->csb_status; 2227 const u8 num_entries = execlists->csb_size; 2228 u8 head, tail; 2229 2230 /* 2231 * As we modify our execlists state tracking we require exclusive 2232 * access. Either we are inside the tasklet, or the tasklet is disabled 2233 * and we assume that is only inside the reset paths and so serialised. 2234 */ 2235 GEM_BUG_ON(!tasklet_is_locked(&execlists->tasklet) && 2236 !reset_in_progress(execlists)); 2237 GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine)); 2238 2239 /* 2240 * Note that csb_write, csb_status may be either in HWSP or mmio. 2241 * When reading from the csb_write mmio register, we have to be 2242 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is 2243 * the low 4bits. As it happens we know the next 4bits are always 2244 * zero and so we can simply masked off the low u8 of the register 2245 * and treat it identically to reading from the HWSP (without having 2246 * to use explicit shifting and masking, and probably bifurcating 2247 * the code to handle the legacy mmio read). 2248 */ 2249 head = execlists->csb_head; 2250 tail = READ_ONCE(*execlists->csb_write); 2251 if (unlikely(head == tail)) 2252 return; 2253 2254 /* 2255 * Hopefully paired with a wmb() in HW! 2256 * 2257 * We must complete the read of the write pointer before any reads 2258 * from the CSB, so that we do not see stale values. Without an rmb 2259 * (lfence) the HW may speculatively perform the CSB[] reads *before* 2260 * we perform the READ_ONCE(*csb_write). 2261 */ 2262 rmb(); 2263 2264 ENGINE_TRACE(engine, "cs-irq head=%d, tail=%d\n", head, tail); 2265 do { 2266 bool promote; 2267 2268 if (++head == num_entries) 2269 head = 0; 2270 2271 /* 2272 * We are flying near dragons again. 2273 * 2274 * We hold a reference to the request in execlist_port[] 2275 * but no more than that. We are operating in softirq 2276 * context and so cannot hold any mutex or sleep. That 2277 * prevents us stopping the requests we are processing 2278 * in port[] from being retired simultaneously (the 2279 * breadcrumb will be complete before we see the 2280 * context-switch). As we only hold the reference to the 2281 * request, any pointer chasing underneath the request 2282 * is subject to a potential use-after-free. Thus we 2283 * store all of the bookkeeping within port[] as 2284 * required, and avoid using unguarded pointers beneath 2285 * request itself. The same applies to the atomic 2286 * status notifier. 2287 */ 2288 2289 ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n", 2290 head, buf[2 * head + 0], buf[2 * head + 1]); 2291 2292 if (INTEL_GEN(engine->i915) >= 12) 2293 promote = gen12_csb_parse(execlists, buf + 2 * head); 2294 else 2295 promote = gen8_csb_parse(execlists, buf + 2 * head); 2296 if (promote) { 2297 struct i915_request * const *old = execlists->active; 2298 2299 GEM_BUG_ON(!assert_pending_valid(execlists, "promote")); 2300 2301 ring_set_paused(engine, 0); 2302 2303 /* Point active to the new ELSP; prevent overwriting */ 2304 WRITE_ONCE(execlists->active, execlists->pending); 2305 2306 /* cancel old inflight, prepare for switch */ 2307 trace_ports(execlists, "preempted", old); 2308 while (*old) 2309 execlists_schedule_out(*old++); 2310 2311 /* switch pending to inflight */ 2312 WRITE_ONCE(execlists->active, 2313 memcpy(execlists->inflight, 2314 execlists->pending, 2315 execlists_num_ports(execlists) * 2316 sizeof(*execlists->pending))); 2317 2318 WRITE_ONCE(execlists->pending[0], NULL); 2319 } else { 2320 GEM_BUG_ON(!*execlists->active); 2321 2322 /* port0 completed, advanced to port1 */ 2323 trace_ports(execlists, "completed", execlists->active); 2324 2325 /* 2326 * We rely on the hardware being strongly 2327 * ordered, that the breadcrumb write is 2328 * coherent (visible from the CPU) before the 2329 * user interrupt and CSB is processed. 2330 */ 2331 if (GEM_SHOW_DEBUG() && 2332 !i915_request_completed(*execlists->active) && 2333 !reset_in_progress(execlists)) { 2334 struct i915_request *rq = *execlists->active; > 2335 const u32 *regs = rq->context->lrc_reg_state; 2336 2337 ENGINE_TRACE(engine, 2338 "ring:{start:0x%08x, head:%04x, tail:%04x, ctl:%08x, mode:%08x}\n", 2339 ENGINE_READ(engine, RING_START), 2340 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR, 2341 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR, 2342 ENGINE_READ(engine, RING_CTL), 2343 ENGINE_READ(engine, RING_MI_MODE)); 2344 ENGINE_TRACE(engine, 2345 "rq:{start:%08x, head:%04x, tail:%04x, seqno:%llx:%d, hwsp:%d}, ", 2346 i915_ggtt_offset(rq->ring->vma), 2347 rq->head, rq->tail, 2348 rq->fence.context, 2349 lower_32_bits(rq->fence.seqno), 2350 hwsp_seqno(rq)); 2351 ENGINE_TRACE(engine, 2352 "ctx:{start:%08x, head:%04x, tail:%04x}, ", 2353 regs[CTX_RING_START], 2354 regs[CTX_RING_HEAD], 2355 regs[CTX_RING_TAIL]); 2356 2357 GEM_BUG_ON("context completed before request"); 2358 } 2359 2360 execlists_schedule_out(*execlists->active++); 2361 2362 GEM_BUG_ON(execlists->active - execlists->inflight > 2363 execlists_num_ports(execlists)); 2364 } 2365 } while (head != tail); 2366 2367 execlists->csb_head = head; 2368 set_timeslice(engine); 2369 2370 /* 2371 * Gen11 has proven to fail wrt global observation point between 2372 * entry and tail update, failing on the ordering and thus 2373 * we see an old entry in the context status buffer. 2374 * 2375 * Forcibly evict out entries for the next gpu csb update, 2376 * to increase the odds that we get a fresh entries with non 2377 * working hardware. The cost for doing so comes out mostly with 2378 * the wash as hardware, working or not, will need to do the 2379 * invalidation before. 2380 */ 2381 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); 2382 } 2383 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

1 0

[PATCH v4 libdrm 1/2] include/drm: sync up drm.h to 3ff4c24bdb1f
by Juston Li 13 Feb '20

13 Feb '20

Adds DRM_IOCTL_MODE_GETFB2 Taken from drm-next-misc: commit 3ff4c24bdb1f494c217c80348f9db4896043ed81 Author: Lyude Paul <lyude(a)redhat.com> Date: Fri Jan 17 17:47:48 2020 -0500 drm/dp_mst: Fix indenting in drm_dp_mst_topology_mgr_set_mst() Signed-off-by: Juston Li <juston.li(a)intel.com> --- include/drm/drm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm.h b/include/drm/drm.h index ab9403397815..c7fd2a35fd7b 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -942,6 +942,8 @@ extern "C" { #define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) +#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) + /** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. -- 2.21.1

4 7

[PATCH 0/4] *** Delay enqueuing context create command ***
by Gurchetan Singh 13 Feb '20

13 Feb '20

Let's delay enqueuing the context creation command until the first 3D ioctl, as we add more context types. This is based on kraxel's "drm/virtio: rework batching" patch and needs that to work correctly. Gurchetan Singh (4): drm/virtio: use consistent names for drm_files drm/virtio: factor out context create cmd drm/virtio: track whether or not a context has been initiated drm/virtio: enqueue virtio_gpu_create_context after first 3D ioctl drivers/gpu/drm/virtio/virtgpu_drv.h | 3 ++ drivers/gpu/drm/virtio/virtgpu_ioctl.c | 46 ++++++++++++++++++++------ drivers/gpu/drm/virtio/virtgpu_kms.c | 11 +++--- 3 files changed, 44 insertions(+), 16 deletions(-) -- 2.25.0.225.g125e21ebc7-goog

3 9

[PATCH] drm/nouveau/kms/gv100-: Re-set LUT after clearing for modesets
by Lyude Paul 12 Feb '20

12 Feb '20

While certain modeset operations on gv100+ need us to temporarily disable the LUT, we make the mistake of sometimes neglecting to reprogram the LUT after such modesets. In particular, moving a head from one encoder to another seems to trigger this quite often. GV100+ is very picky about having a LUT in most scenarios, so this causes the display engine to hang with the following error code: disp: chid 1 stat 00005080 reason 5 [INVALID_STATE] mthd 0200 data 00000001 code 0000002d) So, fix this by always re-programming the LUT if we're clearing it in a state where the wndw is still visible, and has a XLUT handle programmed. Signed-off-by: Lyude Paul <lyude(a)redhat.com> Fixes: facaed62b4cb ("drm/nouveau/kms/gv100: initial support") Cc: <stable(a)vger.kernel.org> # v4.18+ --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 890315291b01..bb737f9281e6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -458,6 +458,8 @@ nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) asyw->clr.ntfy = armw->ntfy.handle != 0; asyw->clr.sema = armw->sema.handle != 0; asyw->clr.xlut = armw->xlut.handle != 0; + if (asyw->clr.xlut && asyw->visible) + asyw->set.xlut = asyw->xlut.handle != 0; asyw->clr.csc = armw->csc.valid; if (wndw->func->image_clr) asyw->clr.image = armw->image.handle[0] != 0; -- 2.24.1

1 0

[PATCH 0/4] drm/nouveau: DP interlace fixes
by Lyude Paul 12 Feb '20

12 Feb '20

Currently, nouveau doesn't actually bother to try probing whether or not it can actually handle interlaced modes over DisplayPort. As a result, on volta and later we'll end up trying to set an interlaced mode even when it's not supported and cause the front end for the display engine to hang. So, let's teach nouveau to reject interlaced modes on hardware that can't actually handle it. Additionally for MST, since we accomplish this by simply reusing more of the SST mode validation we also get (some) basic bw validation for modes we detect on MST connectors completely for free. Lyude Paul (4): drm/nouveau/kms/nv50-: Probe SOR caps for DP interlacing support drm/nouveau/kms/gv100-: Add support for interlaced modes drm/nouveau/kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes() drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST drivers/gpu/drm/nouveau/dispnv50/disp.c | 55 ++++++++++++++------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 5 +- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 5 +- drivers/gpu/drm/nouveau/nouveau_connector.c | 43 ++++++++++------ drivers/gpu/drm/nouveau/nouveau_connector.h | 5 ++ drivers/gpu/drm/nouveau/nouveau_dp.c | 27 ++++++++++ drivers/gpu/drm/nouveau/nouveau_encoder.h | 7 +++ 7 files changed, 108 insertions(+), 39 deletions(-) -- 2.24.1

1 4

[pull] amdgpu 5.6 fixes
by Alex Deucher 12 Feb '20

12 Feb '20

Hi Dave, Daniel, Fixes for 5.6. The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.6-2020-02-12 for you to fetch changes up to e33a8cfda5198fc09554fdd77ba246de42c886bd: drm/amdgpu:/navi10: use the ODCAP enum to index the caps array (2020-02-11 15:42:33 -0500) ---------------------------------------------------------------- amd-drm-fixes-5.6-2020-02-12: amdgpu: - Additional OD fixes for navi - Misc display fixes - VCN 2.5 DPG fix - Prevent build errors on PowerPC on some configs - GDS EDC fix ---------------------------------------------------------------- Alex Deucher (2): drm/amdgpu: update smu_v11_0_pptable.h drm/amdgpu:/navi10: use the ODCAP enum to index the caps array Aric Cyr (1): drm/amd/display: Check engine is not NULL before acquiring Daniel Kolesa (1): amdgpu: Prevent build errors regarding soft/hard-float FP ABI tags Guchun Chen (2): drm/amdgpu: limit GDS clearing workaround in cold boot sequence drm/amdgpu: correct comment to clear up the confusion Isabel Zhang (1): drm/amd/display: Add initialitions for PLL2 clock source James Zhu (2): drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1 drm/amdgpu/vcn2.5: fix warning Jonathan Kim (1): drm/amdgpu: fix amdgpu pmu to use hwc->config instead of hwc->conf Nicholas Kazlauskas (1): drm/amd/display: Don't map ATOM_ENABLE to ATOM_INIT Roman Li (1): drm/amd/display: Fix psr static frames calculation Sung Lee (3): drm/amd/display: Do not set optimized_require to false after plane disable drm/amd/display: Use dcfclk to populate watermark ranges drm/amd/display: DCN2.x Do not program DPPCLK if same value Yongqiang Sun (1): drm/amd/display: Limit minimum DPPCLK to 100MHz. drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 15 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +++++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 14 ++++--- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 8 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++- .../gpu/drm/amd/display/dc/bios/command_table2.c | 4 -- drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 6 +++ .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 20 ++++++---- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 - .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 6 +++ .../gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h | 46 +++++++++++++++------- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 22 +++++------ 16 files changed, 108 insertions(+), 66 deletions(-)

1 0

[PATCH -next] drm/panfrost: Remove set but not used variable 'bo'
by YueHaibing 12 Feb '20

12 Feb '20

Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/panfrost/panfrost_job.c: In function 'panfrost_job_cleanup': drivers/gpu/drm/panfrost/panfrost_job.c:278:31: warning: variable 'bo' set but not used [-Wunused-but-set-variable] commit bdefca2d8dc0 ("drm/panfrost: Add the panfrost_gem_mapping concept") involved this unused variable. Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: YueHaibing <yuehaibing(a)huawei.com> --- drivers/gpu/drm/panfrost/panfrost_job.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c index 7c36ec675b73..ccb8546a9342 100644 --- a/drivers/gpu/drm/panfrost/panfrost_job.c +++ b/drivers/gpu/drm/panfrost/panfrost_job.c @@ -275,12 +275,8 @@ static void panfrost_job_cleanup(struct kref *ref) } if (job->bos) { - struct panfrost_gem_object *bo; - - for (i = 0; i < job->bo_count; i++) { - bo = to_panfrost_bo(job->bos[i]); + for (i = 0; i < job->bo_count; i++) drm_gem_object_put_unlocked(job->bos[i]); - } kvfree(job->bos); }

4 3

[PATCH] drm/panfrost: perfcnt: Reserve/use the AS attached to the perfcnt MMU context
by Boris Brezillon 12 Feb '20

12 Feb '20

We need to use the AS attached to the opened FD when dumping counters. Reported-by: Antonio Caggiano <antonio.caggiano(a)collabora.com> Fixes: 7282f7645d06 ("drm/panfrost: Implement per FD address spaces") Cc: <stable(a)vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon(a)collabora.com> --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 7 ++++++- drivers/gpu/drm/panfrost/panfrost_perfcnt.c | 11 ++++------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index 763cfca886a7..3107b0738e40 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -151,7 +151,12 @@ u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) as = mmu->as; if (as >= 0) { int en = atomic_inc_return(&mmu->as_count); - WARN_ON(en >= NUM_JOB_SLOTS); + + /* + * AS can be retained by active jobs or a perfcnt context, + * hence the '+ 1' here. + */ + WARN_ON(en >= (NUM_JOB_SLOTS + 1)); list_move(&mmu->list, &pfdev->as_lru_list); goto out; diff --git a/drivers/gpu/drm/panfrost/panfrost_perfcnt.c b/drivers/gpu/drm/panfrost/panfrost_perfcnt.c index 684820448be3..6913578d5aa7 100644 --- a/drivers/gpu/drm/panfrost/panfrost_perfcnt.c +++ b/drivers/gpu/drm/panfrost/panfrost_perfcnt.c @@ -73,7 +73,7 @@ static int panfrost_perfcnt_enable_locked(struct panfrost_device *pfdev, struct panfrost_file_priv *user = file_priv->driver_priv; struct panfrost_perfcnt *perfcnt = pfdev->perfcnt; struct drm_gem_shmem_object *bo; - u32 cfg; + u32 cfg, as; int ret; if (user == perfcnt->user) @@ -126,12 +126,8 @@ static int panfrost_perfcnt_enable_locked(struct panfrost_device *pfdev, perfcnt->user = user; - /* - * Always use address space 0 for now. - * FIXME: this needs to be updated when we start using different - * address space. - */ - cfg = GPU_PERFCNT_CFG_AS(0) | + as = panfrost_mmu_as_get(pfdev, perfcnt->mapping->mmu); + cfg = GPU_PERFCNT_CFG_AS(as) | GPU_PERFCNT_CFG_MODE(GPU_PERFCNT_CFG_MODE_MANUAL); /* @@ -195,6 +191,7 @@ static int panfrost_perfcnt_disable_locked(struct panfrost_device *pfdev, drm_gem_shmem_vunmap(&perfcnt->mapping->obj->base.base, perfcnt->buf); perfcnt->buf = NULL; panfrost_gem_close(&perfcnt->mapping->obj->base.base, file_priv); + panfrost_mmu_as_put(pfdev, perfcnt->mapping->mmu); panfrost_gem_mapping_put(perfcnt->mapping); perfcnt->mapping = NULL; pm_runtime_mark_last_busy(pfdev->dev); -- 2.24.1

4 3

[PATCH v2] drm/virtio: rework batching
by Gerd Hoffmann 12 Feb '20

12 Feb '20

Drop the virtio_gpu_{disable,enable}_notify(). Add a new virtio_gpu_notify() call instead, which must be called whenever the driver wants make sure the host is notified needed. Drop notification from command submission. Add virtio_gpu_notify() calls everywhere instead. This results in more batching because we now notify only once for a series of commands. We already had that for page flips, now we also batch resource creation (create + attach-backing), display updates (edid + display-info) and device initialization. With this in place it is also possible to make notification optional for userspace ioctls. v2: - rebase to latest drm-misc-next. - use "if (!atomic_read())". - add review & test tags. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-by: Gurchetan Singh <gurchetansingh(a)chromium.org> Tested-by: Gurchetan Singh <gurchetansingh(a)chromium.org> --- drivers/gpu/drm/virtio/virtgpu_drv.h | 6 ++--- drivers/gpu/drm/virtio/virtgpu_display.c | 2 ++ drivers/gpu/drm/virtio/virtgpu_ioctl.c | 4 ++++ drivers/gpu/drm/virtio/virtgpu_kms.c | 3 +++ drivers/gpu/drm/virtio/virtgpu_object.c | 1 + drivers/gpu/drm/virtio/virtgpu_plane.c | 5 ++-- drivers/gpu/drm/virtio/virtgpu_vq.c | 30 ++++++++++-------------- 7 files changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h index af9403e1cf78..2f6c4ccbfd14 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.h +++ b/drivers/gpu/drm/virtio/virtgpu_drv.h @@ -179,8 +179,7 @@ struct virtio_gpu_device { struct virtio_gpu_queue cursorq; struct kmem_cache *vbufs; - bool disable_notify; - bool pending_notify; + atomic_t pending_commands; struct ida resource_ida; @@ -335,8 +334,7 @@ void virtio_gpu_dequeue_ctrl_func(struct work_struct *work); void virtio_gpu_dequeue_cursor_func(struct work_struct *work); void virtio_gpu_dequeue_fence_func(struct work_struct *work); -void virtio_gpu_disable_notify(struct virtio_gpu_device *vgdev); -void virtio_gpu_enable_notify(struct virtio_gpu_device *vgdev); +void virtio_gpu_notify(struct virtio_gpu_device *vgdev); /* virtio_gpu_display.c */ void virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev); diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c index af953db4a0c9..2b7e6ae65546 100644 --- a/drivers/gpu/drm/virtio/virtgpu_display.c +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -90,6 +90,7 @@ static void virtio_gpu_crtc_mode_set_nofb(struct drm_crtc *crtc) virtio_gpu_cmd_set_scanout(vgdev, output->index, 0, crtc->mode.hdisplay, crtc->mode.vdisplay, 0, 0); + virtio_gpu_notify(vgdev); } static void virtio_gpu_crtc_atomic_enable(struct drm_crtc *crtc, @@ -108,6 +109,7 @@ static void virtio_gpu_crtc_atomic_disable(struct drm_crtc *crtc, struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc); virtio_gpu_cmd_set_scanout(vgdev, output->index, 0, 0, 0, 0, 0); + virtio_gpu_notify(vgdev); output->enabled = false; } diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c b/drivers/gpu/drm/virtio/virtgpu_ioctl.c index 205ec4abae2b..75d818d707e6 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c +++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c @@ -158,6 +158,7 @@ static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, virtio_gpu_cmd_submit(vgdev, buf, exbuf->size, vfpriv->ctx_id, buflist, out_fence); + virtio_gpu_notify(vgdev); return 0; out_memdup: @@ -314,6 +315,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, (vgdev, vfpriv->ctx_id, offset, args->level, &args->box, objs, fence); dma_fence_put(&fence->f); + virtio_gpu_notify(vgdev); return 0; err_unlock: @@ -359,6 +361,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, args->level, &args->box, objs, fence); dma_fence_put(&fence->f); } + virtio_gpu_notify(vgdev); return 0; err_unlock: @@ -445,6 +448,7 @@ static int virtio_gpu_get_caps_ioctl(struct drm_device *dev, /* not in cache - need to talk to hw */ virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver, &cache_ent); + virtio_gpu_notify(vgdev); copy_exit: ret = wait_event_timeout(vgdev->resp_wq, diff --git a/drivers/gpu/drm/virtio/virtgpu_kms.c b/drivers/gpu/drm/virtio/virtgpu_kms.c index 4009c2f97d08..7eabcf1ca424 100644 --- a/drivers/gpu/drm/virtio/virtgpu_kms.c +++ b/drivers/gpu/drm/virtio/virtgpu_kms.c @@ -44,6 +44,7 @@ static void virtio_gpu_config_changed_work_func(struct work_struct *work) if (vgdev->has_edid) virtio_gpu_cmd_get_edids(vgdev); virtio_gpu_cmd_get_display_info(vgdev); + virtio_gpu_notify(vgdev); drm_helper_hpd_irq_event(vgdev->ddev); events_clear |= VIRTIO_GPU_EVENT_DISPLAY; } @@ -92,6 +93,7 @@ static void virtio_gpu_get_capsets(struct virtio_gpu_device *vgdev, } for (i = 0; i < num_capsets; i++) { virtio_gpu_cmd_get_capset_info(vgdev, i); + virtio_gpu_notify(vgdev); ret = wait_event_timeout(vgdev->resp_wq, vgdev->capsets[i].id > 0, 5 * HZ); if (ret == 0) { @@ -205,6 +207,7 @@ int virtio_gpu_init(struct drm_device *dev) if (vgdev->has_edid) virtio_gpu_cmd_get_edids(vgdev); virtio_gpu_cmd_get_display_info(vgdev); + virtio_gpu_notify(vgdev); wait_event_timeout(vgdev->resp_wq, !vgdev->display_info_pending, 5 * HZ); return 0; diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c index 8870ee23ff2b..65d6834d3c74 100644 --- a/drivers/gpu/drm/virtio/virtgpu_object.c +++ b/drivers/gpu/drm/virtio/virtgpu_object.c @@ -224,6 +224,7 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, return ret; } + virtio_gpu_notify(vgdev); *bo_ptr = bo; return 0; diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c b/drivers/gpu/drm/virtio/virtgpu_plane.c index ac42c84d2d7f..fd6487fb0855 100644 --- a/drivers/gpu/drm/virtio/virtgpu_plane.c +++ b/drivers/gpu/drm/virtio/virtgpu_plane.c @@ -154,8 +154,6 @@ static void virtio_gpu_primary_plane_update(struct drm_plane *plane, if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect)) return; - virtio_gpu_disable_notify(vgdev); - bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]); if (bo->dumb) virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect); @@ -187,7 +185,7 @@ static void virtio_gpu_primary_plane_update(struct drm_plane *plane, rect.x2 - rect.x1, rect.y2 - rect.y1); - virtio_gpu_enable_notify(vgdev); + virtio_gpu_notify(vgdev); } static int virtio_gpu_cursor_prepare_fb(struct drm_plane *plane, @@ -265,6 +263,7 @@ static void virtio_gpu_cursor_plane_update(struct drm_plane *plane, plane->state->crtc_w, plane->state->crtc_h, 0, 0, objs, vgfb->fence); + virtio_gpu_notify(vgdev); dma_fence_wait(&vgfb->fence->f, true); dma_fence_put(&vgfb->fence->f); vgfb->fence = NULL; diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c index cfe9c54f87a3..357fef8197dc 100644 --- a/drivers/gpu/drm/virtio/virtgpu_vq.c +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -329,7 +329,6 @@ static void virtio_gpu_queue_ctrl_sgs(struct virtio_gpu_device *vgdev, int incnt) { struct virtqueue *vq = vgdev->ctrlq.vq; - bool notify = false; int ret, idx; if (!drm_dev_enter(vgdev->ddev, &idx)) { @@ -368,16 +367,10 @@ static void virtio_gpu_queue_ctrl_sgs(struct virtio_gpu_device *vgdev, trace_virtio_gpu_cmd_queue(vq, virtio_gpu_vbuf_ctrl_hdr(vbuf)); - notify = virtqueue_kick_prepare(vq); + atomic_inc(&vgdev->pending_commands); spin_unlock(&vgdev->ctrlq.qlock); - if (notify) { - if (vgdev->disable_notify) - vgdev->pending_notify = true; - else - virtqueue_notify(vq); - } drm_dev_exit(idx); } @@ -434,19 +427,20 @@ static void virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev, } } -void virtio_gpu_disable_notify(struct virtio_gpu_device *vgdev) +void virtio_gpu_notify(struct virtio_gpu_device *vgdev) { - vgdev->disable_notify = true; -} + bool notify; -void virtio_gpu_enable_notify(struct virtio_gpu_device *vgdev) -{ - vgdev->disable_notify = false; - - if (!vgdev->pending_notify) + if (!atomic_read(&vgdev->pending_commands)) return; - vgdev->pending_notify = false; - virtqueue_notify(vgdev->ctrlq.vq); + + spin_lock(&vgdev->ctrlq.qlock); + atomic_set(&vgdev->pending_commands, 0); + notify = virtqueue_kick_prepare(vgdev->ctrlq.vq); + spin_unlock(&vgdev->ctrlq.qlock); + + if (notify) + virtqueue_notify(vgdev->ctrlq.vq); } static void virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev, -- 2.18.2

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dri-devel February 2020