dri-devel February 2020

dri-devel@lists.freedesktop.org

302 participants
679 discussions

[PATCH] drm/qxl: replace zero-length array with flexible-array member
by Gustavo A. R. Silva 13 Feb '20

13 Feb '20

The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertenly introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Gustavo A. R. Silva <gustavo(a)embeddedor.com> --- drivers/gpu/drm/qxl/qxl_cmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c index ef09dc6bc635..d1086b2a6892 100644 --- a/drivers/gpu/drm/qxl/qxl_cmd.c +++ b/drivers/gpu/drm/qxl/qxl_cmd.c @@ -36,7 +36,7 @@ static int qxl_reap_surface_id(struct qxl_device *qdev, int max_to_reap); struct ring { struct qxl_ring_header header; - uint8_t elements[0]; + uint8_t elements[]; }; struct qxl_ring { -- 2.25.0

2 1

[PATCH] drm/hisilicon/hibmc: add gamma_set function
by Zhihui Chen 13 Feb '20

13 Feb '20

add gamma_set function, and we can also use it to adjust the brightness of the display. Signed-off-by: Zhihui Chen <chenzhihui4(a)huawei.com> --- .../gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 37 +++++++++++++++++++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h | 5 +++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c index 24de937c1cb1..f1ce6cb099d0 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c @@ -456,6 +456,42 @@ static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc) priv->mmio + HIBMC_RAW_INTERRUPT_EN); } +static void hibmc_crtc_load_lut(struct drm_crtc *crtc) +{ + struct hibmc_drm_private *priv = crtc->dev->dev_private; + void __iomem *mmio = priv->mmio; + u16 *r, *g, *b; + unsigned int reg; + int i; + + r = crtc->gamma_store; + g = r + crtc->gamma_size; + b = g + crtc->gamma_size; + + for (i = 0; i < crtc->gamma_size; i++) { + unsigned int offset = i << 2; + u8 red = *r++ >> 8; + u8 green = *g++ >> 8; + u8 blue = *b++ >> 8; + u32 rgb = (red << 16) | (green << 8) | blue; + + writel(rgb, mmio + HIBMC_CRT_PALETTE + offset); + } + + reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); + reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1); + writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); +} + +static int hibmc_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size, + struct drm_modeset_acquire_ctx *ctx) +{ + hibmc_crtc_load_lut(crtc); + + return 0; +} + static const struct drm_crtc_funcs hibmc_crtc_funcs = { .page_flip = drm_atomic_helper_page_flip, .set_config = drm_atomic_helper_set_config, @@ -465,6 +501,7 @@ static const struct drm_crtc_funcs hibmc_crtc_funcs = { .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, .enable_vblank = hibmc_crtc_enable_vblank, .disable_vblank = hibmc_crtc_disable_vblank, + .gamma_set = hibmc_crtc_gamma_set, }; static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = { diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h index b9e20cfcfb5a..9b7e85947113 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h @@ -91,6 +91,9 @@ #define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8) #define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x100 +#define HIBMC_CTL_DISP_CTL_GAMMA(x) ((x) << 3) +#define HIBMC_CTL_DISP_CTL_GAMMA_MASK 0x08 + #define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2) #define HIBMC_CRT_DISP_CTL_PLANE_MASK 4 @@ -193,5 +196,7 @@ #define CRT_PLL2_HS_148MHZ 0xB0CCCCCD #define CRT_PLL2_HS_193MHZ 0xC0872B02 +#define HIBMC_CRT_PALETTE 0x80C00 + #define HIBMC_FIELD(field, value) (field(value) & field##_MASK) #endif -- 2.20.1

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[PATCH] drm/hisilicon/hibmc: add DPMS on/off function
by Zhihui Chen 13 Feb '20

13 Feb '20

add DPMS function to turn on/off signal of monitor Signed-off-by: Zhihui Chen <chenzhihui4(a)huawei.com> --- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 16 ++++++++++++++++ drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h | 6 ++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c index 722e369f30d4..24de937c1cb1 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c @@ -189,6 +189,20 @@ static struct drm_plane *hibmc_plane_init(struct hibmc_drm_private *priv) return plane; } +static void hibmc_crtc_dpms(struct drm_crtc *crtc, int dpms) +{ + struct hibmc_drm_private *priv = crtc->dev->dev_private; + unsigned int reg; + + reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); + reg &= ~HIBMC_CRT_DISP_CTL_DPMS_MASK; + reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms); + reg &= ~HIBMC_CRT_DISP_CTL_TIMING_MASK; + if (dpms == HIBMC_CRT_DPMS_ON) + reg |= HIBMC_CRT_DISP_CTL_TIMING(1); + writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); +} + static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { @@ -205,6 +219,7 @@ static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, reg |= HIBMC_CURR_GATE_DISPLAY(1); hibmc_set_current_gate(priv, reg); drm_crtc_vblank_on(crtc); + hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_ON); } static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, @@ -213,6 +228,7 @@ static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, unsigned int reg; struct hibmc_drm_private *priv = crtc->dev->dev_private; + hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_OFF); drm_crtc_vblank_off(crtc); hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP); diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h index b63a1ee15ceb..b9e20cfcfb5a 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h @@ -68,6 +68,12 @@ #define HIBMC_CRT_DISP_CTL 0x80200 +#define HIBMC_CRT_DISP_CTL_DPMS(x) ((x) << 30) +#define HIBMC_CRT_DISP_CTL_DPMS_MASK 0xc0000000 + +#define HIBMC_CRT_DPMS_ON 0 +#define HIBMC_CRT_DPMS_OFF 3 + #define HIBMC_CRT_DISP_CTL_CRTSELECT(x) ((x) << 25) #define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK 0x2000000 -- 2.20.1

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[PATCH] drm/hisilicon/hibmc: fix 'xset dpms force off' fail
by Zhihui Chen 13 Feb '20

13 Feb '20

both crtc_state->adjusted_mode.hdisplay and crtc_state->adjusted_mode.vdisplay are 0 when switch dpms off, return -EINVAL cause switch dpms off fail. Signed-off-by: Zhihui Chen <chenzhihui4(a)huawei.com> --- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c index 6527a97f68a3..722e369f30d4 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c @@ -80,6 +80,9 @@ static int hibmc_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } + if (!crtc_state->enable) + return 0; + if (state->crtc_x + state->crtc_w > crtc_state->adjusted_mode.hdisplay || state->crtc_y + state->crtc_h > -- 2.20.1

2 1

[PULL] drm-intel-next-fixes for v5.6-rc2
by Jani Nikula 13 Feb '20

13 Feb '20

Hi Dave & Daniel - Most of these were aimed at a "next fixes" pull already during the merge window, but there were issues with the baseline I used, which resulted in a lot of issues in CI. I've regenerated this stuff piecemeal now, adding gradually to it, and it seems healthy now. Due to the issues this is much bigger than I'd like. But it was obviously necessary to take the time to ensure it's not garbage... BR, Jani. The following changes since commit 9f880327160feb695de03caa29604883b0d00087: Merge tag 'amd-drm-next-5.6-2020-02-05' of git://people.freedesktop.org/~agd5f/linux into drm-next (2020-02-07 12:29:36 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2020-02-13 for you to fetch changes up to 2aaaa5ee1c3d624a5bcad4ee25f954559c565bc2: drm/i915: Mark the removal of the i915_request from the sched.link (2020-02-12 17:04:33 +0200) ---------------------------------------------------------------- drm/i915 fixes for v5.6-rc2 ---------------------------------------------------------------- Chris Wilson (19): drm/i915/pmu: Correct the rc6 offset upon enabling drm/i915/gem: Take local vma references for the parser drm/i915/selftests: Add a mock i915_vma to the mock_ring drm/i915/gt: Use the BIT when checking the flags, not the index drm/i915/execlists: Leave resetting ring to intel_ring drm/i915/gem: Store mmap_offsets in an rbtree rather than a plain list drm/i915: Don't show the blank process name for internal/simulated errors drm/i915/gem: Detect overflow in calculating dumb buffer size drm/i915: Check activity on i915_vma after confirming pin_count==0 drm/i915: Stub out i915_gpu_coredump_put drm/i915: Tighten atomicity of i915_active_acquire vs i915_active_release drm/i915/gt: Acquire ce->active before ce->pin_count/ce->pin_mutex drm/i915/gem: Tighten checks and acquiring the mmap object drm/i915: Keep track of request among the scheduling lists drm/i915/gt: Allow temporary suspension of inflight requests drm/i915/execlists: Offline error capture drm/i915/execlists: Take a reference while capturing the guilty request drm/i915/execlists: Reclaim the hanging virtual request drm/i915: Mark the removal of the i915_request from the sched.link Igor Druzhinin (2): drm/i915/gvt: fix high-order allocation failure on late load drm/i915/gvt: more locking for ppgtt mm LRU list Jani Nikula (1): Merge tag 'gvt-fixes-2020-02-12' of https://github.com/intel/gvt-linux into drm-intel-next-fixes José Roberto de Souza (1): drm/i915: Fix preallocated barrier list append Vandita Kulkarni (1): drm/i915/bios: Fix the timing parameters Ville Syrjälä (2): drm/i915: Fix post-fastset modeset check for port sync drm/i915: Make a copy of the ggtt view for slave plane Vivek Kasireddy (2): drm/i915/dsi: Lookup the i2c bus from ACPI NS only if CONFIG_ACPI=y (v2) drm/i915/dsi: Ensure that the ACPI adapter lookup overrides the bus num Zhang Xiaoxu (1): drm/i915: Fix i915_error_state_store error defination drivers/gpu/drm/i915/display/intel_bios.c | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 44 ++- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 50 ++-- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 37 ++- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 129 ++++++--- drivers/gpu/drm/i915/gem/i915_gem_object.c | 18 +- drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 +- drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 6 +- drivers/gpu/drm/i915/gt/intel_context.c | 46 +-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 354 ++++++++++++++++++++++- drivers/gpu/drm/i915/gt/mock_engine.c | 17 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 258 +++++++++++++++++ drivers/gpu/drm/i915/gvt/firmware.c | 4 +- drivers/gpu/drm/i915/gvt/gtt.c | 4 + drivers/gpu/drm/i915/i915_active.c | 35 ++- drivers/gpu/drm/i915/i915_active.h | 6 + drivers/gpu/drm/i915/i915_gem.c | 5 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.h | 7 +- drivers/gpu/drm/i915/i915_pmu.c | 12 + drivers/gpu/drm/i915/i915_request.c | 6 +- drivers/gpu/drm/i915/i915_request.h | 60 ++++ drivers/gpu/drm/i915/i915_scheduler.c | 22 +- drivers/gpu/drm/i915/i915_vma.c | 14 +- 26 files changed, 990 insertions(+), 178 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center

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[PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP
by Douglas Anderson 13 Feb '20

13 Feb '20

This series contains a pile of patches that was created to support hooking up the AUO B116XAK01 panel to the eDP side of the bridge. In general it should be useful for hooking up a wider variety of DP panels to the bridge, especially those with lower resolution and lower bits per pixel. The overall result of this series: * Allows panels with fewer than 4 DP lanes hooked up to work. * Optimizes the link rate for panels with 6 bpp. * Supports trying more than one link rate when training if the main link rate didn't work. * Avoids invalid link rates. It's not expected that this series will break any existing users but testing is always good. To support the AUO B116XAK01, we could actually stop at the ("Use 18-bit DP if we can") patch since that causes the panel to run at a link rate of 1.62 which works. The patches to try more than one link rate were all developed prior to realizing that I could just use 18-bit mode and were validated with that patch reverted. These patches were tested on sdm845-cheza atop mainline as of 2019-12-13 and also on another board (the one with AUO B116XAK01) atop a downstream kernel tree. This patch series doesn't do anything to optimize the MIPI link and only focuses on the DP link. For instance, it's left as an exercise to the reader to see if we can use the 666-packed mode on the MIPI link and save some power (because we could lower the clock rate). I am nowhere near a display expert and my knowledge of DP and MIPI is pretty much zero. If something about this patch series smells wrong, it probably is. Please let know and I'll try to fix it. Changes in v3: - Init rate_valid table, don't rely on stack being 0 (oops). - Rename rate_times_200khz to rate_per_200khz. - Loop over the ti_sn_bridge_dp_rate_lut table, making code smaller. - Use 'true' instead of 1 for bools. - Added note to commit message noting DP 1.4+ isn't well tested. Changes in v2: - Squash in maybe-uninitialized fix from Rob Clark. - Patch ("Avoid invalid rates") replaces ("Skip non-standard DP rates") Douglas Anderson (9): drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can drm/bridge: ti-sn65dsi86: Group DP link training bits in a function drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail drm/bridge: ti-sn65dsi86: Avoid invalid rates drivers/gpu/drm/bridge/ti-sn65dsi86.c | 259 +++++++++++++++++++++----- 1 file changed, 216 insertions(+), 43 deletions(-) -- 2.24.1.735.g03f4e72817-goog

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[PATCH -next] crypto: ccree - remove set but not used variable 'du_size'
by YueHaibing 13 Feb '20

13 Feb '20

Fixes gcc '-Wunused-but-set-variable' warning: drivers/crypto/ccree/cc_cipher.c: In function 'cc_setup_state_desc': drivers/crypto/ccree/cc_cipher.c:536:15: warning: variable 'du_size' set but not used [-Wunused-but-set-variable] commit 5c83e8ec4d51 ("crypto: ccree - fix FDE descriptor sequence") involved this unused variable, so remove it. Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: YueHaibing <yuehaibing(a)huawei.com> --- drivers/crypto/ccree/cc_cipher.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/crypto/ccree/cc_cipher.c b/drivers/crypto/ccree/cc_cipher.c index 7d6252d892d7..b5133f57bc87 100644 --- a/drivers/crypto/ccree/cc_cipher.c +++ b/drivers/crypto/ccree/cc_cipher.c @@ -533,14 +533,6 @@ static void cc_setup_state_desc(struct crypto_tfm *tfm, int flow_mode = ctx_p->flow_mode; int direction = req_ctx->gen_ctx.op_type; dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr; - unsigned int du_size = nbytes; - - struct cc_crypto_alg *cc_alg = - container_of(tfm->__crt_alg, struct cc_crypto_alg, - skcipher_alg.base); - - if (cc_alg->data_unit) - du_size = cc_alg->data_unit; switch (cipher_mode) { case DRV_CIPHER_ECB:

2 1

[PATCH] drm/bridge: adv7511: Replace hardcoded number
by Fabio Estevam 13 Feb '20

13 Feb '20

The hardcoded '12' means the number of elements in the adv7511_csc_ycbcr_to_rgb[] array, so use the ARRAY_SIZE() macro to let the code less error prone. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index 9e13e466e72c..568c6d52cdda 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -132,6 +132,13 @@ static const struct regmap_config adv7511_regmap_config = { * Hardware configuration */ +/* Coefficients for adv7511 color space conversion */ +static const uint16_t adv7511_csc_ycbcr_to_rgb[] = { + 0x0734, 0x04ad, 0x0000, 0x1c1b, + 0x1ddc, 0x04ad, 0x1f24, 0x0135, + 0x0000, 0x04ad, 0x087c, 0x1b77, +}; + static void adv7511_set_colormap(struct adv7511 *adv7511, bool enable, const uint16_t *coeff, unsigned int scaling_factor) @@ -142,7 +149,7 @@ static void adv7511_set_colormap(struct adv7511 *adv7511, bool enable, ADV7511_CSC_UPDATE_MODE, ADV7511_CSC_UPDATE_MODE); if (enable) { - for (i = 0; i < 12; ++i) { + for (i = 0; i < ARRAY_SIZE(adv7511_csc_ycbcr_to_rgb); ++i) { regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(i), 0x1f, coeff[i] >> 8); @@ -193,13 +200,6 @@ static int adv7511_packet_disable(struct adv7511 *adv7511, unsigned int packet) return 0; } -/* Coefficients for adv7511 color space conversion */ -static const uint16_t adv7511_csc_ycbcr_to_rgb[] = { - 0x0734, 0x04ad, 0x0000, 0x1c1b, - 0x1ddc, 0x04ad, 0x1f24, 0x0135, - 0x0000, 0x04ad, 0x087c, 0x1b77, -}; - static void adv7511_set_config_csc(struct adv7511 *adv7511, struct drm_connector *connector, bool rgb, bool hdmi_mode) -- 2.17.1

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[PATCH 00/14] MIPS: Fixes and improvements for CI20 board (JZ4780)
by H. Nikolaus Schaller 13 Feb '20

13 Feb '20

This patch set provides several improvements for the CI20 board: * suppress warnings from i2c if device is not responding * make ingenic-drm found through DT * allow davicom dm9000 ethernet controller to use MAC address provided by U-Boot * fix #include in jz4780.dtsi * configure for loadable kernel modules * add DTS for IR sensor and SW1 button * configure so that LEDs, IR sensor, SW1 button have drivers * fix DTS for ACT8600 PMU and configure driver * fix interrupt of nxp,pcf8563 There is another patch set in our queue to add HDMI support on top of this work. Signed-off-by: Paul Boddie <paul(a)boddie.org.uk> Signed-off-by: H. Nikolaus Schaller <hns(a)goldelico.com> Alex Smith (1): MIPS: DTS: CI20: add DT node for IR sensor H. Nikolaus Schaller (13): i2c: jz4780: suppress txabrt reports for i2cdetect drm: ingenic-drm: add MODULE_DEVICE_TABLE net: davicom: dm9000: allow to pass MAC address through mac_addr module parameter MIPS: DTS: jz4780: fix #includes for irq.h and gpio.h MIPS: CI20: defconfig: configure for supporting modules MIPS: CI20: defconfig: compile leds-gpio driver into the kernel and configure for LED triggers MIPS: DTS: CI20: fix PMU definitions for ACT8600 MIPS: CI20: defconfig: configure CONFIG_REGULATOR_ACT8865 for PMU MIPS: DTS: CI20: give eth0_power a defined voltage. MIPS: CI20: defconfig: compile gpio-ir driver MIPS: DTS: CI20: add DT node for SW1 as Enter button MIPS: CI20: defconfig: configure for CONFIG_KEYBOARD_GPIO=m MIPS: DTS: CI20: fix interrupt for pcf8563 RTC arch/mips/boot/dts/ingenic/ci20.dts | 71 ++++++++++++++++++++------ arch/mips/boot/dts/ingenic/jz4780.dtsi | 2 + arch/mips/configs/ci20_defconfig | 21 ++++++++ drivers/gpu/drm/ingenic/ingenic-drm.c | 2 + drivers/i2c/busses/i2c-jz4780.c | 3 ++ drivers/net/ethernet/davicom/dm9000.c | 42 +++++++++++++++ 6 files changed, 125 insertions(+), 16 deletions(-) -- 2.23.0

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[PATCH] drm/mediatek: fix race condition of plugged_cb and codec_dev
by Tzung-Bi Shih 13 Feb '20

13 Feb '20

hdmi_conn_detect and mtk_hdmi_audio_hook_plugged_cb woule be called by different threads. plugged_cb and codec_dev are in danger of race condition. Fixes by: - Checks NULLs first. - Uses WRITE_ONCE() to prevent store tearing (i.e. write to plugged_cb after codec_dev). - Uses codec_dev as a signal to report HDMI jack status. The patch intends to not use mutex to protect the shared variables. In runtime, mtk_hdmi_audio_hook_plugged_cb would be called only once if no one rebinds the sound card. In contrast, hdmi_conn_detect could be called multiple times. Uses a mutex within hdmi_conn_detect calling path is a waste (no lock contention). Fixes: 5d3c64477392 ("drm/mediatek: support HDMI jack status reporting") Signed-off-by: Tzung-Bi Shih <tzungbi(a)google.com> --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 03aeb73005ef..746567c91bb7 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1201,7 +1201,7 @@ mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi) { bool connected = mtk_cec_hpd_high(hdmi->cec_dev); - if (hdmi->plugged_cb && hdmi->codec_dev) + if (hdmi->codec_dev) hdmi->plugged_cb(hdmi->codec_dev, connected); return connected ? @@ -1669,8 +1669,12 @@ static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data, { struct mtk_hdmi *hdmi = data; - hdmi->plugged_cb = fn; - hdmi->codec_dev = codec_dev; + if (!fn || !codec_dev) + return -EINVAL; + + /* Use WRITE_ONCE() to prevent store tearing. */ + WRITE_ONCE(hdmi->plugged_cb, fn); + WRITE_ONCE(hdmi->codec_dev, codec_dev); mtk_hdmi_update_plugged_status(hdmi); return 0; -- 2.25.0.225.g125e21ebc7-goog

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dri-devel February 2020